Chapter 3 SCSP Function

■ 3.1 Interface

SCSP has two built-in CPU (main CPU and sound CPU) interfaces.
The priority is higher on the main CPU interface, so the processing speed of the sound CPU depends on the operation of the main CPU.

● Sound CPU interface

A sound CPU interface is a block that specializes in functions so that a sound CPU can be connected. By providing this interface, the sound CPU can be connected to the SCSP without any external circuit.
The sound CPU program resides in sound memory. Therefore, all CPU programs are located in the address space of the sound CPU.

● Main CPU interface

The access between the interfaces with the main CPU is shown in Figure 3.1.

Figure 3.1 Access overview

The interface starts when the select signal (MCCSN) from the main CPU falls, and ends when the select signal rises. Also, if "1" is output to the ready signal (MCRDYN) to the main CPU, the select signal (MCCSN) from the main CPU and the data bus (MCD [7: 0]) of the main CPU do not change.

● Precautions when interface with the main CPU

• Read and write in 16-bit units (word units).
  → 8-bit units (byte units) cannot be accessed from the main CPU.

• When there is a read / write request, the address and data are fetched into the buffer in SCSP. As a result, "1" is output to the ready signal (MCRDYN) to the main CPU and a wait is generated. This wait continues until the processing inside the LSI is completed, so do not use continuous writing, which causes frequent occurrence of weights, except when the power is turned on.

• When the power is turned on, the time required to initialize the sound memory by continuous writing is approximately 100 msec with 4 Mbit DRAM.

■ 3.2 Memory access control

When accessing sound memory from SCSP, the following priorities are maintained.

1. PCM data read by PCM sound source, access by DSP
2. DRAM refresh cycle
3. DMA transfer
4. Access by main CPU
5. Access by sound CPU

If there are high-priority access requests, the low-priority access requests are weighted. In addition, the determination of which device memory access is permitted for the device requesting memory access (PCM sound source section, DSP section, main CPU, sound CPU, DMA, etc.) is based on the fact that memory access is actually performed. Since it was done before, no higher ranking access request will occur while executing a lower ranking access request.

Figure 3.2 Memory access priority

SCSP / Sound CPU performance is determined by the memory cycle allocation.
The memory cycle is performed 128 times between 1 sample (1 / 44.1K ≒ 22.68 μsec), and these 128 times are distributed to each device. Since the number of CPU accesses varies depending on the application, there is no best way to access memory, but please note the following points.

● Notes on memory access

• Since the sound memory uses DRAM, a refresh cycle is required.
  The Saturn sound system requires two free cycles per sample, so other devices can use 126 memory cycles.

• The sound source and DSP memory cycles have the highest priority memory cycle.

• Since the sound source uses two memory cycles per slot sound, a total of 64 memory cycles are used for a maximum of 32 slots.
  When the EG is in the maximum attenuation state ("3FFH"), the sound source does not access the memory. Set KEY_OFF for slots that do not output audio.

• The DSP makes up to 64 memory accesses. This depends on the DSP application. If you want to temporarily store data in the DSP, use the registers inside the DSP as much as possible.

• If you are using DMA with built-in SCSP, the sound CPU will have a considerable weight, which will slow down the sound CPU.