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SCSP User's Manual / 4.1 Register Map

■ Control register for each slot

The slot-specific control registers represent the register allocations configured in each of the 32 slots (SLOT0 to SLOT31).

Table 4.1 Address map by slot
slot
SLOT		 address slot
SLOT		 address
 0
 100000H ~ 100017H
 16
 100200H-100217H
 1
 100020H ~ 100037H
 17
 100220H-100237H
 2
 100040H ~ 100057H
 18
 100240H-100257H
 3
 100060H ~ 100077H
 19
 100260H-100277H
 Four
 100080H ~ 100097H
 20
 100280H-100297H
 Five
 1000A0H ~ 1000B7H
 twenty one
 1002A0H ~ 1002B7H
 6
 1000C0H ~ 1000D7H
 twenty two
 1002C0H ~ 1002D7H
 7
 1000E0H ~ 1000F7H
 twenty three
 1002E0H ~ 1002F7H
 8
 100100H-100117H
 twenty four
 100300H-100317H
 9
 100120H-100137H
 twenty five
 100320H-100337H
 Ten
 100140H-100157H
 26
 100340H-100357H
 11
 100160H-100177H
 27
 100360H-100377H
 12
 100180H-100197H
 28
 100380H-100397H
 13
 1001A0H ~ 1001B7H
 29
 1003A0H ~ 1003B7H
 14
 1001C0H ~ 1001D7H
 30
 1003C0H ~ 1003D7H
 15
 1001E0H ~ 1001F7H
 31
 1003E0H ~ 1003F7H

Indicates each register in one slot.

Notation example:
Start address: SA [19:16] indicates that a 4-bit statement from the 16th bit to the 19th bit of SA is assigned.

Table 4.2 Control registers by slot
address MSB --- --- --- --- --- --- --- --- --- --- --- --- --- --- LSB
+ 00h --- --- --- KX KB SBCTL SSCTL LPCTL 8B SA [19:16]
+ 02h SA [15: 0]
+ 04h LSA [15: 0]
+ 06h LEA [15: 0]
+ 08h D2R [4: 0] D1R [4: 0] HO AR [4: 0]
+ 0Ah --- LS KRS [3: 0] DL [4: 0] RR [4: 0]
+ 0Ch --- --- --- --- --- --- SI SD TL [7: 0]
+ 0Eh MDL [3: 0] MDXSL [5: 0] MDYSL [5: 0]
+ 10h --- OCT [3: 0] --- FNS [9: 0]
+ 12h RE LFO [4: 0] PLFOWS PLFOS [2: 0] ALFOWS ALFOS [2: 0]
+ 14h --- --- --- --- --- --- --- --- --- ISEL [3: 0] IMXL [2: 0]
+ 16h DISDL [2: 0] DIPAN [4: 0] EFSDL [2: 0] EFPAN [4: 0]

Listing 4.1 Control registers by slot

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