■ 4.3 Operand execution method

The DSP actually controls and executes the registers in this way for the following instructions.

◆ Execution of JUMP instruction

This is achieved by storing the jump destination address (Immediate Data) in the program RAM address of the program control port. However, please note that the prefetched instruction will be executed. The conditional JUMP instruction first checks the state of the flag of the program control port, and if the condition is met, stores the jump destination address in the program RAM address of the program control port. For the instruction format, refer to the JUMP instruction section in Section 4.5, "Instructions". Figure 4.2 shows the JUMP instruction execution flow.

Figure 4.2 Execution of JUMP instruction

◆ Execution of LOOP program

The program between the address specified in the top address register ([TOP]) and the DSP BTM instruction (see Section 4.5 "Instruction", LOOP BOTTOM instruction) repeats the number of times specified by the loop counter ([LOP]). It will be executed. Therefore, in order to realize this processing, set the value in the top address register or loop counter in advance before executing it. The value can be set by the Load immediate instruction of DSP (see Section 4.5 "Instructions", Load immediate instruction). Figure 4.3 shows the execution flow of the LOOP program.

Figure 4.3 Executing the LOOP program

◆ Execution of DMA instruction

This section describes the process of actually performing DMA transfer by setting the register of the DMA controller from the DSP. DMA instructions can be divided into the following two types according to the transfer direction (read / write).

1. Data transfer from D0 bus to DSP
2. Data transfer from DSP to D0 bus

● Data transfer from D0 bus to DSP

The DSP data RAM transfer start address and the external memory transfer start address are set in the registers ([CT0-3] and [RA0]), and the transfer is started by the DMA instruction. The instruction format up to the DMA instruction is as follows.
See Section 4.5, " Instruction Details " for more information.

MOV SImm, [CT0]; DSP data RAM0 transfer start address set MVI Imm, [RA0]; external memory transfer start address set DMA D0, [MD0], SImm; DMA transfer start using D0 bus

Table 4.6 summarizes the features of this DMA transfer. Since DMA transfer is executed in units of 1 longword, set the number of transfer words (SImm of the DMA instruction above) in units of longwords.

Table 4.1 Features of data transfer from D0 bus to DSP

Item	feature
Set of flags	The TO flag of the program control port is set.
Start and end	Follows an external data ready signal. By this signal, it is transferred in units of one longword. In addition, the DMA transfer is terminated by the end signal from the outside, and the TO flag of the program control port is reset at this timing.
Address update	For each longword transfer, the DSP data RAM transfer address ([CTO-3]) is added by 1, and the external memory transfer address ([RA0]) is added according to the number of added addresses.
Hold state	When the Hold bit of the DMA instruction (see Section 4.5, "Instructions", DMA Instructions) is set to 1, The value at the start of transfer is retained for the number of transfer words ([TN0]) and the external memory transfer address ([RA0]).

● Data transfer from DSP to D0 bus

The DSP data RAM transfer start address and the external memory transfer start address are set in the registers ([CT0-3] and [WA0]), and the transfer is started by the DMA instruction. The instruction format up to the DMA instruction is as follows. See Section 4.5, " Instruction Details " for more information.

MOV SImm, [CT0]; DSP data RAM0 transfer start address set MVI Imm, [WA0]; external memory transfer start address set DMA [MD0], D0, SImm; DMA transfer start using D0 bus

Table 4.7 summarizes the features of this DMA transfer. Since DMA transfer is executed in units of 1 longword, set the number of transfer words (SImm of the DMA instruction above) in units of longwords.

Table 4.2 Features of data transfer from DSP to D0 bus

Item	feature
Set of flags	The TO flag of the program control port is set.
Start and end	Follows an external data ready signal. By this signal, it is transferred in units of one longword. In addition, the DMA transfer is terminated by the end signal from the outside, and the TO flag of the program control port is reset at this timing.
Address update	For each longword transfer, the DSP data RAM transfer address ([CTO-3]) is added by 1, and the external memory transfer address ([WAO]) is added according to the number of added addresses.
Hold state	When the Hold bit of the DMA instruction (see Section 4.5, "Instructions", DMA Instructions) is set to 1, The value at the start of transfer is retained for the number of transfer words ([TN0]) and the external memory transfer address ([WA0]).

◆ Execution of END instruction

When the END instruction is recognized, the program RAM address addition processing of the program control port is stopped, and the program execution control bit (EX flag) is reset. This will stop the execution of the DSP program. However, the data transfer by the DMA instruction continues to be executed until the transfer is completed regardless of this END instruction. The value of the program address when the program is stopped stops at the address next to the address where the END instruction is stored.