★ HARDWARE Manual ★ SMPC User's Manual Figure 3.1 Block diagram of SMPC control mode
Figure 3.2 SMPC control mode setting example
Register name | Set value | Contents |
IOSEL1 / 2 | 0H | SMPC control mode |
EXL1 / 2 | 0H | PAD interrupt, VDP2 external latch disabled |
DDR1 / 2 | 00H | All bit input |
Request to issue | Reception conditions | SMPC operation | |
Continue | break | ||
× | × | on hold | Waiting for request |
× | ○ | break | Peripheral data collection interrupted, INTBACK command terminated |
○ | × | Continue | Continued peripheral data collection |
○ | ○ | Ban | No guarantee |
Figure 3.3 All peripheral data acquisition sequence
Figure 3.4 Peripheral data acquisition cancellation sequence due to break request
★ HARDWARE Manual ★ SMPC User's Manual