<13/54> VDP1 User's Manual / 4.2 Framebuffer switching mode register

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VDP1 User's Manual / Chapter 4 System Registers

■ 4.2 Frame buffer switching mode register

The frame buffer change register (FBCR) controls the drawing and display switching of the frame buffer and the drawing of the double-dense interlace. A write-only 16-bit register located at address 100002H. After turning on the power or resetting, the value will be undefined, so be sure to set the switching mode. Set the unused bit to 0.

FBCR 100002H (W) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 0 0 0 EOS DIE DIL FCM FCT

Frame buffer change mode bits: frame buffer change mode (FCM), bit1

Frame buffer change trigger bit: frame buffer change trigger (FCT), bit0

Normally, two framebuffers use one as the front side and the other as the back side. Display the front side and draw on the back side. Then, after one frame switching time has passed, the front and back sides are toggled. The front side that was displayed becomes the back side that is drawn, and the back side that was drawn becomes the front side that is displayed. The framebuffer can only be accessed by the drawing side. It cannot be displayed. Since the number of characters that can be drawn in one frame is limited, if you want to draw many characters, set it to manual mode and control erase and change from the CPU. When arbitrary data is written from the CPU to the FBCR, the FCM and FCT values are updated inside VDP1 at the time of field change. In manual mode, the FCT bit setting is valid only for the next frame. At the time of frame change, the contents of FCT are updated internally. Set FCM and FCT immediately after the V blank OUT interrupt. Access is prohibited from the first H blank IN interrupt after the V blank OUT interrupt to the next H blank IN interrupt.

FBCR 100002H (W)	bit15	bit14	bit13	bit12	bit11	bit10	bit9	bit8	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
0	0	0	0	0	0	0	0	0	0	0	EOS	DIE	DIL	FCM	FCT

VBE	FCM	FCT	Switching mode	Switching time
0	0	0	1 cycle mode	Change every 1/60 second
0	0	1	Setting prohibited	−
0	1	0	Manual mode (erase)	Erase in the next field
0	1	1	Manual mode (change)	Change in the next field
1	0	0	Setting prohibited	−
1	0	1	Setting prohibited	−
1	1	0	Setting prohibited	−
1	1	1	Manual mode (erase & change)	Erase with V blank, Change in the next field

1 cycle mode

Normal mode. One frame automatically switches every 1/60 second. Set the VBE and FCT bit values to 0.

Erase (manual mode)

The erase light of one frame is controlled from the CPU. Specify the manual erase write of the frame buffer by writing to the registers of VBE = 0, FCM = 1, and FCT = 0. The next field you specify erases the display framebuffer and clears the display framebuffer. The drawing and display framebuffers are not switched. Since the display frame buffer is cleared when erasing is performed, it is necessary to switch between drawing and display by specifying a change in the next field where erasing is specified. Use this mode when there are two or more fields and one frame, such as double-dense interlacing. Also, when switching from manual mode to 1-cycle mode, use this erase in the field before the switch. Erase is used when you know that you will make a frame change in the next field. If you don't know the frame change up to the previous field, use Erase & Change.

Change (manual mode)

The switching of one frame is controlled from the CPU. Switching is specified by writing to the registers of VBE = 0, FCM = 1, and FCT = 1. The next specified field switches between drawing and displaying. There is no erase write, so you need to specify the erase in the field just before you specify the change to erase the framebuffer. You can draw the character on the back side until you instruct to switch. This change is typically used when switching from 1-cycle mode to manual mode. You can also use this change to switch the framebuffer in manual mode.

Erase & Change (Manual Mode)

By setting VBE = 1 in the register, V blank erase is specified, and by setting FCM = 1 and FCT = 1, the frame buffer switching after V blank is specified. It is used when the frame change is unknown until the previous V blank, such as when the frame buffer is not switched until the CPU processing is completed. Once VBE = 1 is set, erase write is automatically performed even at the next V blank, so set VBE = 0 after the frame change and before the next V blank. Set the erase and change immediately after the V blank IN interrupt. If it is set to any other value, it may not be erased and may change. If it is normal, high resolution, and the timing of the frame change is known in advance like interlace, specify erase and change and perform erase light during the display period. In this case, the entire display screen can be erased.

● Sequence when using erase & change

Set VBE = 0, FCM = 1, FCT = 1. Wait for the end of processing such as CPU without setting TV mode selection and FB switching mode. If CPU processing is completed by the H blank IN interrupt (224th line when displaying 224 lines, 240th line when displaying 240 lines) immediately before V blank, VBE = 1, FCM = 1, FCT = 1 ( Erase & Change) is set. Set the erase and change immediately after the V blank IN interrupt. After the V-blank IN interrupt is complete, V-blank erase will begin. At the end of the V blank, the erase light is interrupted and the frame is changed. If the erase light is not completed, erase the unerased part with polygons. Immediately after the V blank OUT interrupt, return VBE to 0 and stop the V blank erase. Return to (2).

● Usage example

The following is an example of using the framebuffer switching mode.

Table 4.3 (a) Example of using frame buffer switching mode (fixed to VBE = 0)

Set value * 1		* 2 Framebuffer 0	* 2 Framebuffer 1	Frame buffer switching mode	Switching time
FCM	FCT	* 2 Framebuffer 0	* 2 Framebuffer 1	Frame buffer switching mode	Switching time
0	0	drawing	Display + erase light	1 cycle mode	60 frames / sec
		Display + erase light	drawing
		drawing	Display + erase light
		Display + erase light	drawing
1	1	drawing	Display + erase light	Manual mode (change) * 3
		display	drawing		20 frames / sec
1	0	display	drawing	Manual mode (erase) * 4
1	1	Display + erase light	drawing	Manual mode (change) * 4
		drawing	display
1	0	drawing	display	Manual mode (erase) * 5
0	0	drawing	Display + erase light	1 cycle mode
		Display + erase light	drawing		60 frames / sec
		drawing	Display + erase light		60 frames / sec

[note]

* 1 V Blank OUT This is the value to be written to the register immediately after the interrupt.

* 2 Switches from the beginning of the field

* 3 Change to switch from 1 cycle mode to manual mode.

* 4 Please be sure to specify erase and change in succession.

* 5 Specify erase in the field immediately before switching to 1-cycle mode.

Table 4.3 (b) Example of using frame buffer switching mode (using VBE)

Dense interlace enable bits: double interlace enable (DIE), bit3

Double-density interlaced drawing line: double interlace plot line (DIL) , bit2

Monodense interlacing displays the same picture in even and odd fields. Double-dense interlace, on the other hand, doubles the vertical resolution by displaying different pictures (only even and odd lines are drawn, respectively) in even / odd fields. With DIE = 1, double-dense interlacing is enabled. The content of the initial display screen after changing the DIE is not guaranteed. For double-dense interlacing, set FCM = FCT = 0 (1 cycle mode) to switch fields every 1/60 second.

DIE	DIL	Interlaced mode	Drawing after the next frame change
0	0	Non-interlaced / Monodense interlacing	All line drawing
0	1	Setting prohibited	−
1	0	Dense interlace	Draw only even (EVEN) lines
1	1	Dense interlace	Draw only odd (ODD) lines

Figure 4.1 Display of single-dense interlace and double-dense interlace

● Display of single-dense interlace ● Display of double-dense interlace　
┌────────┐ ┌────────┐　
│ 0 line ├────────┐ │ 0 line ├────────┐
├────────┤ 0 line │ ├────────┤ 1 line │
│ 1 line ├────────┤ │ 2 lines ├────────┤
├────────┤ 1 line │ ├────────┤ 3 lines │
│ 2 lines ├────────┤ │ 4 lines ├────────┤
├────────┤ 2 lines │ ├────────┤ 5 lines │
│ 3 lines ├────────┤ │ 6 lines ├────────┤
└────────┤ 3 lines │ └────────┤ 7 lines │
└────────┘ └────────┘
・ It looks like 256 lines vertically ・ It looks like 512 lines vertically　
・ Frame change every 1/60 second ・ Even number in each frame buffer　
Draw the same twice or draw only (or odd) lines　
Frame change every 1/30 second　
(Instructed by the CPU using a 1/60 second signal)

Even / odd coordinate selection bit: even / odd coordinate select bit ( EOS), bit4

This bit is enabled when High Speed Shrink (HSS) is set to 1 for rectangular or deformed sprites. If HSS = 1 is specified, the line whose drawing magnification is <1 will be drawn by sampling only the pixels of either even or odd coordinates of the original picture data. This bit specifies whether to sample even or odd coordinates.
When EOS = 0, only pixels with even coordinates are sampled. When EOS = 1, only pixels with odd coordinates are sampled.
If HSS = 0 is specified, this bit will not be referenced.
For details, refer to " High Speed Shrink " in "6.3 Drawing Mode Words".

EOS	Even / odd coordinate selection bits
0	Sampling only even-coordinated pixels
1	Sampling only odd-numbered pixels

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