- When the dot color data of the sprite and each scroll screen is in palette format, the color RAM address is obtained by adding the value of the color RAM address offset register to the dot color data composed of the palette number and dot color code. Outputs color data as dot color data. In the case of RGB format, the dot color data composed of each RGB data is output as it is as the color data of the dots.
When the dot color data on the scroll screen is in palette format, you can specify whether to use the special priority function or special color calculation function by the value of the lower 4 bits of the dot color data. ■ 10.1 Palette format dot color data
- The dot color data in palette format is 11-bit data, and the value of the color RAM address offset register of the corresponding screen is added to the upper 3 bits to obtain the color RAM address that stores the color data of that dot.
● Sprite dot color data
- The palette format sprite dot color data depends on the specified sprite type. When a sprite type with 10 bits or less of dot color data is specified, the missing high-order bit is fixed to 0, the color RAM address offset value for the sprite is added to the high-order 3 bits, and the color RAM address of that dot is specified. will do. If the color RAM mode is set to mode 0 or mode 2, the most significant bit of the color RAM address is ignored.
- The palette-formatted sprite dot color data is shown in Figure 10.1, and the sprite color RAM address is shown in Figure 10.2.
- Figure 10.1 Sprite dot color data in palette format
- ◆ For sprite type 0-3, 5
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- ◆ For sprite types 4 and 6
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Dot color data 10 bits |
|---|
- ◆ For sprite type 7
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | Dot color data 9 bits |
|---|
- ◆ For sprite types C to F
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | Dot color data 8 bits |
|---|
- ◆ For sprite type 8
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | Dot color data 7 bits |
|---|
- ◆ For sprite types 9 to B
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | Dot color data 6 bits |
|---|
- Figure 10.2 Sprite color RAM address
- ・ Sprite dot color data
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- -Color RAM address offset for sprites
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Offset value
3 bits | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|---|
- -Color RAM address of the dot
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Color RAM address 11 bits |
|---|
- [note]
- If the color RAM mode is mode 0 or mode 2 , the most significant bit (LSB) of the color RAM address is ignored.
● Scroll dot color data
- The scroll dot color data in palette format depends on the specified number of character colors. The color RAM address offset value corresponding to each surface is added to the upper 3 bits of the 11-bit dot color data to obtain the color RAM address of that dot. If the color RAM mode is set to mode 0 or mode 2, the most significant bit of the color RAM address is ignored.
- Since there is no corresponding color RAM address offset value on the line color screen, the 11-bit value read from the line color screen table becomes the color RAM address as it is.
- Figure 10.3 shows the scroll dot color data in palette format, and Figure 10.4 shows the color RAM address of the scroll screen.
- Figure 10.3 Scroll dot color data in palette format
- ◆ When the number of character colors is 16
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Palette number
7 bits | Dot color code
4 bits |
|---|
- ◆ When the number of character colors is 256
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Palette number
3 bits | Dot color code
8 bits |
|---|
- ◆ When the number of character colors is 2048
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Dot color data
11 bits |
|---|
- Figure 10.4 Scroll color RAM address
- ・ Scroll dot color data
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Dot color data 11 bits |
|---|
- -Color RAM address offset for each scroll
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Offset value
3 bits | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|---|
- -Color RAM address of the dot
Ten | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Color RAM address 11 bits |
|---|
- [note]
- If the color RAM mode is mode 0 or mode 2 , the most significant bit (LSB) of the color RAM address is ignored.
● Color RAM address offset register
- The color RAM address offset register specifies the color RAM address offset value for the sprite and each scroll screen. This is a write-only 16-bit register located at addresses 1800E4H to 1800E6H. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.
- CRAOFA 1800E4H
- CRAOFB 1800E6H
15 | 14 | 13 | 12 | 11 | Ten | 09 09 | 08 08 |
--- | --- | --- | --- | --- | --- | --- | --- |
|---|
- Color RAM address offset bit : Color RAM address offset bit
- (N0CAOS2 to N0CAOS0, N1CAOS2 to N1CAOS0, N2CAOS2 to N2CAOS0, N3CAOS2 to N3CAOS0, R0CAOS2 to R0CAOS0, SPCAOS2 to SPCAOS0)
Specifies the color RAM address offset value for sprites and each scroll screen.| N0CAOS2 to N0CAOS0 | 1800E4H | Bits 2-0 | For NBG0 (or for RBG1) |
| N1CAOS2 to N1CAOS0 | 1800E4H | Bits 6-4 | For NBG1 (or for EXBG) |
| N2CAOS2 to N2CAOS0 | 1800E4H | Bits 10-8 | For NBG2 |
| N3CAOS2 to N3CAOS0 | 1800E4H | Bits 14-12 | For NBG3 |
| R0CAOS2 to R0CAOS0 | 1800E6H | Bits 2-0 | For RBG0 |
| SPCAOS2 to SPCAOS0 | 1800E6H | Bits 6-4 | For sprites |
- The actual color RAM address offset value is calculated by the following formula: If the color RAM mode is mode 0 or mode 2, the most significant bit of the color RAM address resulting from the addition of the color RAM address offset values is ignored.
- -When the color RAM mode is mode 0 or mode 1
(Color RAM address offset value)
= (Color RAM address offset register value 3 bits) x 200H
- -When the color RAM mode is mode 2
(Color RAM address offset value)
= (Color RAM address offset register value 3 bits) x 400H
