2.2 Data specifications

[Low level SCU]

List

Title Data specifications

Data DMA channel

Data name none

No 1

Use the following constants when specifying the DMA channel of the SCU.

constant	explanation
DMA_SCU_CH0	Channel 0
DMA_SCU_CH1	Channel 1
DMA_SCU_CH2	Channel 2

List

Title Data specifications

Data Transfer parameters

Data name DmaScuPrm

No 2

The transfer parameters have the following structure.

struct {
     Uint32 dxr; / * Read address * /
     Uint32 dxw; / * Write address * /
     Uint32 dxc; / * Number of bytes transferred * /
     Uint32 dxad_r; / * Read address addition value * /
     Uint32 dxad_w; / * Write address addition value * /
     Uint32 dxmod; / * mode bit * /
     Uint32 dxrup; / * Read address update bit * /
     Uint32 dxwup; / * Write address update bit * /
     Uint32 dxft; / * Start factor selection bit * /
     Uint32 msk; / * Mask bit * /
} DmaScuPrm;

The following are the constants that can be used with each of these members.

dxad_r / * Read address addition value * /

constant	explanation
DMA_SCU_R0	Do not add
DMA_SCU_R4	Add 4 bytes

dxad_w / * Write address addition value * /

constant	explanation
DMA_SCU_W0	Do not add
DMA_SCU_W2	Add 2 bytes
DMA_SCU_W4	Add 4 bytes
DMA_SCU_W8	Add 8 bytes
DMA_SCU_W16	Add 16 bytes
DMA_SCU_W32	Add 32 bytes
DMA_SCU_W64	Add 64 bytes
DMA_SCU_W128	Add 128 bytes

dxmod / * mode bit * /

constant	explanation
DMA_SCU_DIR	Direct mode
DMA_SCU_IN_DIR	Indirect mode

dxrup / * Read address update bit * /
dxwup / * Write address update bit * /

constant	explanation
DMA_SCU_KEEP	Hold
DMA_SCU_REN	Update

dxft / * Start factor selection bit * /

constant	explanation
DMA_SCU_F_VBLK_IN	V-blank-IN signal reception
DMA_SCU_F_VBLK_OUT	V-blank-OUT signal reception
DMA_SCU_F_HBLK_IN	H-Blank-IN signal reception
DMA_SCU_F_TIM0	Timer 0 signal reception
DMA_SCU_F_TIM1	Timer 1 signal reception
DMA_SCU_F_SND	Sound-Receive Req signal
DMA_SCU_F_SPR	Sprite drawing end signal reception
DMA_SCU_F_DMA	Set of DMA activation factor bits

mask / * mask bit * /

The member write mask bit. Only the bits specified by the following constants are written (set). Multiple specifications by OR are possible.

constant	explanation
DMA_SCU_M_DXR	Read address
DMA_SCU_M_DXW	Write address
DMA_SCU_M_DXC	Number of bytes transferred
DMA_SCU_M_DXAD_R	Read address addition value
DMA_SCU_M_DXAD_W	Write address addition value
DMA_SCU_M_DXMOD	Mode bit
DMA_SCU_M_DXRUP	Read address update bit
DMA_SCU_M_DXWUP	Write address update bit
DMA_SCU_M_DXFT	Start factor selection bit

List

Title Data specifications

Data status

Data name DmaScuStatus

No 3

The status is the following structure.

struct {
    	Uint32 dxmv;
        }

The following are the constants that can be used with each of these members.

dxmv / * DMA operation flag * /

constant	explanation
DMA_SCU_MV	in action
DMA_SCU_NO_MV	Not in operation

[Low level CPU]

List

Title Data specifications

Data DMA channel

Data name none

No Four

Use the following constants when specifying the DMA channel of the CPU.

constant	explanation
DMA_CPU_CH0	Channel 0
DMA_CPU_CH1	Channel 1

List

Title Data specifications

Data Common transfer parameters

Data name DmaCpuComPrm

No Five

The common transfer parameter has the following structure.

struct {
     Uint32 pr; / * Priority mode * /
     Uint32 dme; / * DMA master enabled * /
     Uint32 msk; / * Mask bit * /
} DmaCpuComPrm;

The following are the constants that can be used with each of these members.

pr / * Priority mode * /

constant	explanation
DMA_CPU_FIX	Fixed priority
DMA_CPU_ROR	Priority depends on round robin

 dme / * DMA master enabled * /

constant	explanation
DMA_CPU_DIS	Prohibit DMA transfer on all channels
DMA_CPU_ENA	Allow DMA transfer for all channels

 msk / * mask bit * /

The member write mask bit. Only the bits specified by the following constants are written (set). Multiple specifications by OR are possible.

constant	explanation
DMA_CPU_M_PR	Priority mode
DMA_CPU_M_AE	Address error flag
DMA_CPU_M_NMIF	NMI flag
DMA_CPU_M_DME	DMA master enabled

List

Title Data specifications

Data Transfer parameters

Data name DmaCpuPrm

No 6

The transfer parameters have the following structure.

struct {
     Uint32 sar; / * DMA source address * /
     Uint32 dar; / * DMA destination address * /
     Uint32 tcr; / * DMA transfer count * /
     Uint32 dm; / * Destination address mode * /
     Uint32 sm; / * Source address mode bit * /
     Uint32 ts; / * Transfer size * /
     Uint32 ar; / * Auto request mode * /
     Uint32 ie; / * Interrupt enable * /
     Uint32 drcr; / * DMA request / response selection control * /
     Uint32 msk; / * Mask bit * /
} DmaCpuPrm;

The following are the constants that can be used with each of these members.

dm / * Destination address mode * /
sm / * source address mode bits * /

constant	explanation
DMA_CPU_AM_NOM	Fixed
DMA_CPU_AM_ADD	gain
DMA_CPU_AM_SUB	Decrease

ts / * Transfer size * /

constant	explanation
DMA_CPU_1	Byte unit
DMA_CPU_2	Word (2 bytes) unit
DMA_CPU_4	Long word (4 bytes) unit
DMA_CPU_16	16 bytes

 ar / * Auto request mode * /

constant	explanation
DMA_CPU_MOD	Module request
DMA_CPU_AUTO	Art request

 ie / * interrupt enable * /

constant	explanation
DMA_CPU_INT_ENA	Allow interrupt request
DMA_CPU_INT_DIS	Disable interrupt request

 drcr / * DMA request / response selection control * /

constant	explanation
DMA_CPU_DREQ	DREQ (external request)
DMA_CPU_RXI	RXI (Built-in SCI received data full interrupt transfer request)
DMA_CPU_TXI	TXI (Built-in SCI transmit data empty interrupt transfer request)

 msk / * mask bit * /

The member write mask bit. Only the bits specified by the following constants are written (set). Multiple specifications by OR are possible.

constant	explanation
DMA_CPU_M_SAR	DMA source address
DMA_CPU_M_DAR	DMA destination address
DMA_CPU_M_TCR	DMA transfer count
DMA_CPU_M_DM	Destination address mode
DMA_CPU_M_SM	Source address mode bits
DMA_CPU_M_TS	Transfer size
DMA_CPU_M_AR	Auto request mode
DMA_CPU_M_IE	Interrupt enable
DMA_CPU_M_DRCR	DMA request / response selection control
DMA_CPU_M_TE	Transfer end flag