guide

■ Explanation

● Register / reference operation of interrupt processing routine

After booting from the BOOT ROM, the interrupt vector table of the master SH2 is at the beginning of the work RAM, and the VBR (vector base register) points to this address.
The interrupt vector table of the slave SH2 is the beginning of the work RAM + 400H, and the VBR of the slave SH2 points to that address.

The interrupt vector (programmable) of each SH2 built-in module is assigned by default as shown in the table below. In addition, a dummy routine that does nothing is set in the vector table. (However, illegal instructions and address error exceptions are infinite loops.)

An FRT input capture interrupt is assigned for master-slave communication and has an initial priority of 15 (highest priority).

In the table below, the priority of each interrupt except the FRT input capture interrupt is set to 0, and interrupts are not permitted.
To change the interrupt priority of the built-in module, the contents of the interrupt control register must be changed as required by the application.

Master SH2 vector initialization	Slave SH2 vector initialization
40H ~ SCU interrupt vector 5FH (fixed by hardware)	41H H Blank In ** 43H V Blank In
60H SCI reception error 61H SCI receive buffer full 62H SCI send buffer empty 63H SCI transmission end * 64H FRT input capture 65H FRT compare match 66H FRT overflow 67H unused 68H WDT interval 69H BSC compare match 6AH unused 6BH unused 6CH DMACH1 (built-in SH2) 6DH DMACH0 (with built-in SH2) 6EH DIVU (division) 6FH unused	60H SCI reception error 61H SCI receive buffer full 62H SCI send buffer empty 63H SCI transmission end * 64H FRT input capture 65H FRT compare match 66H FRT overflow 67H unused 68H WDT interval 69H BSC compare match 6AH unused 6BH unused 6CH DMACH1 (built-in SH2) 6DH DMACH0 (with built-in SH2) 6EH DIVU (division) 6FH unused
* Slave → For master passing	* For master → slave passing ** IRL2, IRL6 level interrupt

Use this operation routine to register an interrupt processing routine in the interrupt vector and to refer to the current processing routine address.
For SCU interrupts on the master side, there is an SCU interrupt routine that implements interrupt processing in the form of calling a C function as a subroutine, and you can register the C function there or refer to the registered address. increase.

Functions registered in the SCU interrupt routine will be called each time an interrupt occurs. Before and after the call, register save and restore are performed according to the register save rules of the SHC compiler. Therefore, any C function, or routine that follows its rules, can be registered and processed. However, it may not be suitable for interrupt processing that requires a fast response, such as H blank In.
If you register another interrupt handling routine in the SCU interrupt vector, the SCU interrupt handling routine is bypassed and disabled.

● SCU interrupt mask set / reference / change operation

Since the mask value set in the SCU interrupt mask register cannot be read from this register, it is not possible to perform operations on the actually set value when making changes.
Therefore, a service routine that stores this value separately in memory and updates it consistently with the actual SCU interrupt mask register is provided.
When using it, the library or application must always set / change the SCU interrupt mask via these functions.
Furthermore, after setting / changing the SCU interrupt mask register, the SCU interrupt status register and, if necessary, the A-Bus interrupt acknowledge register are subsequently cleared.

● Simple semaphore operation

We provide a service that allows you to use the memory (256 bytes) provided by BOOT ROM as 256 simple semaphores.
The first half of the semaphore (numbers 0 to 127) can be used freely. The second half (128-255) is for operations related to the library.
If the library uses certain features, such as DMA, set the semaphore's MSB (80H) to 1 to indicate that it is in use. It also clears the MSB after use, indicating that it is free.
Normally, in a process that requires a resource to be secured for a relatively long time, you should decide the procedure for operating and referencing the semaphore so that the interrupt processing that occurs between them does not access the resource without permission.
For the semaphore memory, the SH2 TAS instruction is used when the MSB is set. This instruction is inseparable in execution (it does not release the bus right), so only one operation can ensure that the semaphore can be acquired.
You must release the semaphore once you have acquired it.
At reset, all semaphore memory is released (cleared).

● System clock switching

System clock switching cannot be performed by issuing a single command to SMPC. Use of this system program is essential.

• CPU clock 26MHz ← → 28MHz
• Horizontal resolution 320/640 ← → 352/704

Switching the system clock involves resetting to some hardware.

Device to be reset	OFF or non-warranty device	Unaffected device
SCU VDP1 VDP2 SCSI / SCC (development machine only)	Slave SH (OFF) DRAM (previous content destruction) SCSP (OFF)	Master SH * Note SDRAM CD SIMM (development machine only)

*note

Since the master SH goes into standby mode during clock switching, the FRT and SCI of the SH built-in modules need to be reset. The WDT is used in this process. In addition, after processing, there is NMI, for example, the control of DMAC is suspended by NMI. Refer to the SH manual and perform the process to restart the process if necessary.

About re-initialization process after reset

SCU ...

Reinitialize bus, interrupt mask, etc. However, the value of SYS_GETSCUIM is used for the interrupt mask value.

About post-processing required by the application

VDP2 ...

You need to set the TV mode relatively quickly. Since the device itself will be in 320/640 mode after reset, especially when the system clock is changed to 352/704 mode, the sync signal may be out of sync with the TV and the screen may be disturbed.

VDP1,2 & SCSP ...

All previous settings are invalid. It needs to be reset.

SMPC ...

Hot reset is always enabled.

The clock change processing time is about 110ms. This is because it includes the device reset time.

● SCU interrupt routine priority change

The BOOT ROM has an interrupt priority management table for the SCU interrupt processing service, and its rewriting is possible.

	This is a dangerous service and can cause your system to hang if there are conflicting priority relationships in the table contents! !! !!

This allows you to optimize interrupt handling (using SYS_SETUINT) for your application.
To do this, the application should have data with the same structure as the table and call SYS_CHGUIPR.
The table has 32 longwords, and 1 longword has the following contents.

SH2 SR lower word value

SCU interrupt mask lower word value

Value set in SR at the start of interrupt processing

A value that is ORed with the current mask setting value and written to the SCU interrupt mask register at the start of interrupt processing.

This longword position in the table corresponds to the SCU's 30 interrupt factors.
(V-Blank In is the first, V-Blank Out is the second, ... but including the free space of 2 longwords corresponding to vectors 4EH and 4FH)
In practice, you must take the utmost care in creating the table so that the SR / SCU interrupt mask and the interrupt factor are consistent.
For example, BOOT ROM uses the following table as the default value.

Uint32 PRITab [32] = { 0x00F0FFFF, / * VBI SR = 15 All prohibited (highest priority) 0x00E0FFFE, / * VBO SR = 14 Only VBI allowed 0x00D0FFFC, / * HBI SR = 13 VBI, VBO allowed ・ ・ 0x0070FE00 / * External 15 SR = 7 Mask all 7 or less with specific priority of SCU interrupt / * A Bus interrupt specific priority is 7, 4, 1 for each factor, but it is set to 7 because it is a shared 1-bit mask. };

* / * / * / * / * /

As an example of creation, the SR value is always set to 0, and the priority (priority relationship) is described using only the SCU mask value. In this case, SH can always accept interrupts, and only the SCU mask controls the enable / disable.

Uint32 PRITab [32] = { 0x0000FFF9, / * VBI processing, HBI, VBO permission 0x0000FFFB, / * VBO processing, HBI only permission 0x0000FFFF, / * HBI processing, all prohibited (highest priority) ・ ・ 0x00000000 / * Allow all 15 external processes (lowest priority) };

* / * / * / * /

Contrary to the above example, it is prohibited to mask interrupts at the SR value level without changing the SCU mask value! !! !! (Only 0 or 15 is possible)

In the above example, the interrupt enable / disable register for each built-in module must be operated for interrupt enable / disable of the SH built-in module.

When an interrupt of a certain factor of SCU is enabled and the interrupt occurs, the SR mask of SH is higher than the specific level of the interrupt (value determined by SCU hardware), and the interrupt is rejected by SH. If it can never happen, it's OK. (However, as an exception, SR mask 15 can be completely prohibited)

● CD multiplayer startup execution

A service that starts and executes a CD multiplayer when the application is closed. When you call this service, the CD multiplayer screen is displayed and you can operate it, regardless of the state in which it was called, just like starting the power-on sequence.
It does not return to the caller.

● Power-on clear memory operation

It provides 8 bytes of memory on SDRAM managed by BOOT ROM.
These 8 bytes are initialized to 0 at power-on startup, but are retained by the reset button (NMI).