DMA

A-BUS → C-BUS transfer using CPU-DMA does not work.

Q)

I am using CPU DMA to transfer from ABUS to CBUS (Work RAM-L), but it seems that the second and subsequent transfers have failed.
The number of transfers obtained by CDC_DATAEnd returns to a normal value in the first transfer, but the value of 5 words is always returned in the second and subsequent transfers, and even one byte has not been transferred to the transfer destination.
The routine is described below, but is there any processing required before transfer?

A)

Add DMA_CPU_M_TE to the parameter DmaC.msk passed to the DMA_CpuSetPrm function.
Detail is,

SH7095 Hardware Manual Chapter 9 Direct Memory Access Controller 9.2.4 DMA Channel Control Registers 0, 1

Please refer to.

Cannot transfer between the same buses using SCU-DMA.

Q)

With DMA_ScuMemCopy (), copying between WORK_RAM_H does not work properly.
What could be the reason?

A)

SCU-DMA is a DMA that transfers between different buses.
It cannot be done in the same space.
Use CPU-DMA or software transfer for data transfer in the same space.

<Transfer example that can use SCU-DMA>

WorkRAM-H ← → VDP1
WorkRAM-H ─ → VDP2
WorkRAM-H ← → SCSP (SoundRAM)
CD Buffer ─ → WorkRAM-H
CD Buffer ─ → VDP1
CD Buffer ─ → VDP2
CD Buffer ─ → SCSP (SoundRAM)

Transfer from HighRAM to B-Bus does not work with SCU-DMA.

Q)

I am trying to transfer from work RAM-H to B-BUS using 2ch of SCU DMA in indirect mode, but it is not transferred at all.
Please tell us what the possible causes are.

A)

What is the SCU indirect mode table setting?
Set in the order of "number of bytes transferred", "write address", and "read address".

├───────────────┤
│ Number of bytes transferred for the first time │ m ← Set in the write address register ├─────────────── ┤ Address │ First write address │ m + 4　
├───────────────┤　
│ 1st read address │ m + 8　
├───────────────┤
│: │
│: │
│: │
│: │
├───────────────┤
│ nth number of bytes transferred │
├───────────────┤
│ nth write address │
├─┬─────────────┤
│ 1 │ nth read address │
└─┴─────────────┘
↑
Be sure to set "1" to the 31st bit of the nth read address. 

SCU-DMA indirect mode table specifications.

Q)

The specification of the SCU-DMA indirect mode table is that if the table size is up to 1020 bytes, the start address is placed on the 1024-byte boundary, but what happens if the data exceeds 1020 bytes?
It seems that it is currently operating on a 1024-byte boundary (currently a table of about 2688 bytes). Does this mean that it is not guaranteed in the future?

A)

According to the SCU Additional Manual (No. 25), a data table of 2 ^ m bytes is required when the data size is up to (n × 12) bytes. In other words, the data size currently used there is (2 ^ 11) = 2048 <2688 = (224 x 12) <= 2688 <4096 = (2 ^ 12), so a table size of 4096 bytes is required. It becomes.

About the limit during level 1 startup in DMA.

Q)

SCU-DMA says that DMA level 2 activation is prohibited while DMA level 1 is being executed. Does this only prohibit level 2 activation when DMA level 1 is operating (during DMA transfer)?

If DMA level 1 is auto-started with SCU interrupts, does it mean that level 1 is running all the time?

There is a malfunction, but what are the specific symptoms?
Is it okay to use it if there is no problem with the game?

A)

This is prohibited.
If you start Level 2 when Level 1 is executed, unexpected things will occur and normal operation cannot be guaranteed.
If you use it, please change the program.

About simultaneous use channel of SCU-DMA.

Q)

It is said that there are 2 channels that can be used simultaneously with SCU-DMA, and if 3 channels are used at the same time, the priority will be ignored. Does this mean that all 3 channels will always end just because the priority is ignored?

What is the specific order if the priorities are ignored?

Also, this overlaps with the previous question, but if the priority is ignored, if level 1 is started while level 2 is starting, will malfunction etc. occur in that case?

A)

Please do not use it as it is a hardware prohibition.

Which is the fastest way to transfer from LowRAM to VDP1?

Q)

I would like to use the WORK_RAM_L area as a buffer for sprite data. What is the fastest transfer method from the WORK_RAM_L area to the SPR_VRAM area?
It seems that SCU_DMA cannot be used, so I would like to use CPU_DMA.

A)

The fastest way to transfer from the WORK_RAM_L area is to use CPU-DMA transfer, depending on the amount transferred.
If the transfer volume is small (several bytes), a memory transfer may be better because the DMA transfer has a weight of several clocks before and after startup.