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SCU DSP Arambra Instruction Manual

'94 / 07/08

table of contents

1. Assembler function
2. Execution of assembler
3. Program description format
4. Instruction list
5. Sample program

1. Outline of assembler function

This assembler is for generating the instruction code for DSP, and is intended to be operated on MS-DOS and UNIX. The output code is Motorola's S format, and the code is output directly, so no link is required.
The DSP assembler requires a lot of knowledge about the hardware, so please familiarize yourself with the DSP hardware before using the assembler.

2. Execution of assembler

dspam [option] <source file name>
  1. The following can be specified for the option. (File creation is only at the end of normal)
    -l [filename]: List output specification
    -a [file name]: Specify data format output for SH assembler
    -c [file name]: C language data format output specification
    -m: Specified when using the MODEL M development environment
  2. The source file name does not have a default extension.
  3. The error is displayed only for the first one detected, so repeat the correction and assembly until the error disappears.

3. Program description format

[Label] [△ Operation [△ Operand]]… [Comment]
Example: LABEL: MOV MC0, X; Comment

(1) Label

(2) Operation

(3) Operand

(4) Comment

* Notes on description * About reserved words * About numerical calculation

Arithmetic relation

+… Addition
--… Subtraction
*… Multiplication
/… Division
%… Exclusion
~… Bit negation
&… Bit product
|… Bit sum
^… Exclusive bit sum
<<… Left shift
>>… Right shift

Priority

1. +-~ (unary operator)
2. * /%
3. +-
4. <<>>
Five. &
6. | ^

4. Instruction list

  1. Arithmetic instructions
    NOP AND OR XOR ADD SUB AD2 SR RR SL RL RL8 CLR MOV
  2. Load immediate instruction
    MVI
  3. DMA command
    DMA DMAH
  4. JUMP instruction
    JMP
  5. LOOP BOTTOM instruction
    BTM LPS
  6. END command
    END ENDI

Pseudo-instruction

5. Sample program

(1) When copying the contents of the internal RAM 0 of the DSP to the internal RAM 1.

; ------- sample (1) start -------

COPY_SIZE = 12; Copy size RAM0_ADR = $ 00; Copy source address RAM1_ADR = $ 00; Copy destination address MOV RAM0_ADR, CT0; Set the copy source address of RAM0 MOV RAM1_ADR, CT1; Set the copy destination address of RAM1 MOV COPY_SIZE-1, LOP ; Set transfer size -1 to LOP register LPS; Execution of 1 instruction loop MOV MC0, MC1; Transfer from RAM0 to RAM1 ENDI

; ------- sample (1) end -------

(2) When calculating 2x3 + 4x5. (RAM0 x RAM1 + RAM0 x RAM1 = RAM2) (sample 2b is an optimized version of 2a.)

; ------- sample (2a) start -------

RAM0_ADR = $ 00; 2, 4 Storage address start RAM1_ADR = $ 00; 3, 5 Storage address start RAM2_ADR = $ 00; Result storage address MOV RAM0_ADR, CT0; Set RAM0 address MOV RAM1_ADR, CT1; Set RAM1 address MVI # 2 , MC0; RAM0 set to "2" MVI # 3, MC1; RAM1 set to "3" MVI # 4, MC0; RAM0 set to "4" MVI # 5, MC1; RAM1 set to "5" MOV RAM0_ADR, CT0; set RAM0 address MOV RAM1_ADR, CT1; set RAM1 address MOV RAM2_ADR, CT2; set RAM2 address MOV MC0,X; transfer data from RAM0 to RX MOV MC1, Y; from RAM1 to RY Data transfer to MOV MUL, P; RX and RY integration results stored in PH, PL MOV MC0, X; Data transfer from RAM0 to RX MOV MC1, Y; Data transfer from RAM1 to RY CLR A; ACH, ACL AD2 MOV ALU, A; PH, PL and ACH, ACL addition result is stored in ACH, ACL MOV MUL, P; RX and RY integration result is stored in PH, PL AD2 MOV ALL, MC2 ; PH, PL and ACH, ACL addition result stored in RAM2 ENDI

; ------- sample (2a) end -------
; ------- sample (2b) start -------

RAM0_ADR = $ 00; 2, 4 Storage address start RAM1_ADR = $ 00; 3, 5 Storage address start RAM2_ADR = $ 00; Result storage address MOV RAM0_ADR, CT0
	                                                 MOV RAM1_ADR, CT1
	MVI # 2, MC0
	MVI # 3, MC1
	MVI # 4, MC0
	MVI # 5, MC1
	                                                 MOV RAM0_ADR, CT0
	                                                 MOV RAM1_ADR, CT1
	     MOV MC0, X MOV MC1, Y MOV RAM2_ADR, CT2
	     MOV MC0, X MOV MUL, P MOV MC1, Y CLR A
	AD2 MOV MUL, P MOV ALU, A
	AD2 MOV ALL, MC2
	ENDI

; ------- sample (2b) end -------

(3) When calculating the movement process for the matrix. (RAM0 x RAM1 = RAM2)

 / M00 M01 M02 M03 \ / 100x \ / M00 M01 M02 M03 \
| M10 M11 M12 M13 || 010y | → | M10 M11 M12 M13 |
 \ M20 M21 M22 M23 / | 001z | \ M20 M21 M22 M23 /
 \ 0001 /

; ------- sample (3) start -------

DATA_TOP = $ 10000 >> 2; External memory address is in 4-byte units MAT_SIZE = $ 0C; Array size RAM0_ADR = $ 00; Start address RAM1_ADR = $ 00 that stores the amount of movement of X, Y, Z; Array address RAM2_ADR = $ 00; Address of the original array; (Transfer the array with the movement amount set to RAM0 from the external memory)
;
	MVI DATA_TOP, RA0
	                                                 MOV RAM0_ADR, CT0
	DMA D0, MC0, # $ 02
;
(Copy of array to operate from RAM2 to RAM1)
	                                                 MOV RAM2_ADR, CT2
	                                                 MOV RAM1_ADR, CT1
	                                                 MOV MAT_SIZE-1, LOP
	LPS
	                                                 MOV MC2, MC1
WAITING:
	JMP T0, WAITING
;
(Calculation execution of array)
	                                                 MOV RAM0_ADR, CT0
	                                                 MOV RAM1_ADR, CT1
	     MOV MC0, X MOV MC1, Y 
	     MOV MC0, X MOV MUL, P MOV MC1, Y CLR A
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
	AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM2_ADR + 3, CT2
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y CLR A MOV ALL, MC2
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
	AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM2_ADR + 7, CT2
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y CLR A MOV ALL, MC2
	AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
	AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
	AD2 MOV MUL, P MOV ALU, A MOV RAM2_ADR + 11, CT2
	AD2 MOV ALL, MC2
	ENDI

; ------- sample (3) end -------
that's all
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