DMA instruction

DMA D0, [RAM], SImm

DMA transfer (D0 [31-0] → RAM)

Operation content

D0 [31-0] Transfer data to RAM. The external address register and the forwarding word number register are updated (added) according to the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMA D0, [Destination], Counter

Source = M0 to M3 *

Instruction code

31			28											17	16	15						9	8	7							0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	0	0	0	0	0	x	x	Imm data

Bit data Addition mode choice bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

Bit data Choice limb bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It becomes T0; 1. ** **

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3).

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA64.

If the address addition number is omitted, the addition number will be 1.

DMA [RAM], D0, SImm

DMA transfer (RAM → D0 [31-0])

Operation content

Transfer RAM data to D0 [31-0]. The external address register and the forwarding word number register are updated (added) according to the address addition number. However, for A-Bus, only addition numbers 0 and 1 are valid, and the writing unit is 32 bits. For B-Bus, it is valid for all (addition number 0-64). The writing unit is 16 bits, and 32 bit data is divided into two and written at 16 bit x (0-64) intervals. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMA [Source], D0, Counter

Source = M0 to M3 *

Instruction code

31			28											17	16	15						9	8	7							0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	0	0	1	0	0	x	x	Imm data

Bit data Addition mode choice bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

Bit data Choice limb bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It becomes T0; 1. ** **

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3).

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA64.

If the address addition number is omitted, the addition number will be 1.

DMA D0, [RAM], [s]

DMA transfer (D0 [31-0] → RAM)

Operation content

The data of [s] specified by bit0 to 2 is used as the transfer counter, and the indicated number of D0 [31-0] data is transferred to RAM. The external address register and the forwarding word number register are updated (added) according to the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMA D0, [Destination], [Counter]

Counter = M0 ~ M3 * , MC0 ~ MC3 * ,

Destination = M0 to M3 * , PR *

Instruction code

bit15	Addition mode choice
0	Address addition 0
1	Address addition 1

31			28													15					Ten	9	8						2	1	0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	0	0	x	0	1	0	0	x	x	x	−	−	−	−	−	x	x	x

Bit data Choice limb bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGARM RAM

Bit data [s] Selected limbs bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0, CT0 ++ 1 0 1 DATA RAM1, CT1 ++ 1 1 0 DATA RAM2, CT2 ++ 1 1 1 DATA RAM3, CT3 ++

flag

It becomes T0; 1. ** **

It is incremented only when CTx (x = 0 to 3); b2 = 1. It does not change when b2 = 0.

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3). MCx (x = 0 to 3) selects DATA RAMx (x = 0 to 3) and increments CTx (x = 0 to 3) after transfer.

For PR, select PROGRAM RAM.

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA1.

If the address addition number is omitted, the addition number will be 1.

DMA [RAM], D0, [s]

DMA transfer (RAM → D0 [31-0])

Operation content

The data of [s] specified by bit0 to 2 is used as the transfer counter, and the RAM data is transferred to the D0 [31-0] data by the indicated number. The external address register and the forwarding word number register are updated (added) according to the address addition number. However, for A-Bus, only addition numbers 0 and 1 are valid, and the writing unit is 32 bits. For B-Bus, it is valid for all (addition number 0-64). The writing unit is 16 bits, and 32 bit data is divided into two and written at 16 bit x (0-64) intervals. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMA [Source], D0, [Counter]

Counter = M0 ~ M3 * , MC0 ~ MC3 * ,

Source = M0 to M3 *

Instruction code

Bit data Addition mode choice bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

Bit data [s] Selected limbs bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0, CT0 ++ 1 0 1 DATA RAM1, CT1 ++ 1 1 0 DATA RAM2, CT2 ++ 1 1 1 DATA RAM3, CT3 ++

31			28											17	16	15						9	8						2	1	0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	0	1	1	0	0	x	x	−	−	−	−	−	x	x	x

Bit data		[RAM] Choices
bit9	bit8
0	0	DATA RAM0
0	1	DATA RAM1
1	0	DATA RAM2
1	1	DATA RAM3

flag

It becomes T0; 1. ** **

It is incremented only when CTx (x = 0 to 3); b2 = 1. It does not change when b2 = 0.

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3). MCx (x = 0 to 3) selects DATA RAMx (x = 0 to 3) and increments CTx (x = 0 to 3) after transfer.

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA1.

If the address addition number is omitted, the addition number will be 1.

DMAH D0, [RAM], SImm

DMA transfer in HOLD state (D0 [31-0] → RAM)

Operation content

D0 [31-0] Transfer data to RAM. The external address register and the transfer word number register hold the value at the start of transfer in the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMAH DO, [Destination], Counter

Distination = M0 ~ M3 * , PR *

Instruction code

31			28											17		15					Ten	9	8	7							0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	0	0	x	1	0	0	0	x	x	x	SImm data

bit15 Addition mode choice 0 Address addition 0 1 Address addition 1

Bit data Choice limb bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGRAM RAM

flag

It becomes T0; 1. ** **

remarks

* For Mx (x = 0-3), select DATA RAMx (x = 0-3).

For PR, select PROGRAM RAM.

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMAH0 to DMAH1.

If the address addition number is omitted, the addition number will be 1.

DMAH [RAM], D0, SImm

DMA transfer in HOLD state (RAM → D0 [31-0])

Operation content

Transfer RAM data to D0 [31-0]. The external address register and the transfer word number register hold the value at the start of transfer in the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMAH [Source], DO, Counter

Source = M0 to M3 *

Instruction code

31			28											17	16	15						9	8	7							0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	1	0	1	0	0	x	x	SImm data

Bit data Addition mode choice bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

Bit data Choice limb bit9 bit8 0 0 DATA RAM0 0 1 DATA RAM1 1 0 DATA RAM2 1 1 DATA RAM3

flag

It becomes T0; 1. ** **

remarks

* For Mx (x = 0-3), select DATA RAMx (x = 0-3).

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMAH0 to DMAH64.

If the address addition number is omitted, the addition number will be 1.

DMAH D0, [RAM], [s]

DMA transfer in HOLD state (D0 [31-0] → RAM)

Operation content

The data of [s] specified by bit0 to 2 is used as the transfer counter, and the indicated number of D0 [31-0] data is transferred to RAM. The external address register and the transfer word number register hold the value at the start of transfer in the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMAH D0, [Destination], [Counter]

Counter = M0 ~ M3 * , MC0 ~ MC3 *

Destination = M0 to M3 * , PR *

Instruction code

bit15	Addition mode choice
0	Address addition 0
1	Address addition 1

31			28													15					Ten	9	8	7					2	1	0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	0	0	x	1	1	0	0	X	x	x	−	−	−	−	−	x	x	x

Bit data [RAM] Choices bit10 bit9 bit8 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 PROGRAM RAM

Bit data [s] Selected limbs bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0, CT0 ++ 1 0 1 DATA RAM1, CT1 ++ 1 1 0 DATA RAM2, CT2 ++ 1 1 1 DATA RAM3, CT3 ++

flag

It becomes T0; 1. ** **

It is incremented only when CTx (x = 0 to 3); b2 = 1. It does not change when b2 = 0.

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3). MCx (x = 0 to 3) selects DATA RAMx (x = 0 to 3) and increments CTx (x = 0 to 3) after transfer.

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA1.

If the address addition number is omitted, the addition number will be 1.

DMAH [RAM], d0, [s]

DMA transfer in HOLD state (RAM → D0 [31-0])

Operation content

The data of [s] specified by bit0 to 2 is used as the transfer counter, and the RAM data is transferred to the D0 [31-0] data by the indicated number. The external address register and the transfer word number register hold the value at the start of transfer in the address addition number. The transfer word number register is a register that stores the number of transfer words in units of long words. The transfer ends when the number of words becomes 0 or is forcibly terminated.

Descriptive formula

label: DMAH [Source], D0, [Counter]

Counter = M0 ~ M3 * , MC0 ~ MC3 *

Source = M0 to M3 *

Instruction code

Bit data Addition mode choice bit17 bit16 bit15 0 0 0 Address addition 0 0 0 1 Address addition 1 0 1 0 Address addition 2 0 1 1 Address addition 4 1 0 0 Address addition 8 1 0 1 Address addition 16 1 1 0 Address addition 32 1 1 1 Address addition 64

Bit data [s] Selected limbs bit2 bit1 bit0 0 0 0 DATA RAM0 0 0 1 DATA RAM1 0 1 0 DATA RAM2 0 1 1 DATA RAM3 1 0 0 DATA RAM0, CT0 ++ 1 0 1 DATA RAM1, CT1 ++ 1 1 0 DATA RAM2, CT2 ++ 1 1 1 DATA RAM3, CT3 ++

31			28											17	16	15						9	8						2	1	0
1	1	0	0	−	−	−	−	−	−	−	−	−	−	x	x	x	1	1	1	0	0	x	x	−	−	−	−	−	x	x	x

Bit data		[RAM] Choices
bit9	bit8
0	0	DATA RAM0
0	1	DATA RAM1
1	0	DATA RAM2
1	1	DATA RAM3

flag

It becomes T0; 1. ** **

It is incremented only when CTx (x = 0 to 3); b2 = 1. It does not change when b2 = 0.

remarks

* For [Mx (x = 0-3)], select DATA RAMx (x = 0-3). MCx (x = 0 to 3) selects DATA RAMx (x = 0 to 3) and increments CTx (x = 0 to 3) after transfer.

** When an END signal is input to notify the end of transfer from the outside, T0; 0 is set.

To specify the address addition, add the addition number after the instruction, and it becomes DMA0 to DMA1.

If the address addition number is omitted, the addition number will be 1.