Chapter 2 Address Map

■ 2.1 Address map

The address maps for VRAM, framebuffer, and system registers managed by VDP1 are as follows:

The addresses described in this chapter are relative addresses unless otherwise specified. Add 5C00000H to find the absolute address.

Figure 2.1 Address map

       * 3　
       ┌───────────┐　
       │ │ * 1　
       │ │　
000000H ~ 07FFFFH │ VRAM │　
       │ 4Mbit │　
       │ │ * 2　
       ├───────────┼──────────┐
       │ │ │
080000H ~ 0BFFFFH │ Frame buffer 0 │ Frame buffer 1 │
       │ 2Mbit │ 2Mbit │
       ├───────────┼──────────┘
0C0000H ~ 0FFFFFH │ Reservation │　
       ├───────────┤　
       │ │　
       │ │　
100000H ~ 17FFFFH │ System register │　
       │ │　
       │ │　
       ├───────────┤　
       │ │　
       │ │　
180000H ~ 1fFFFFH │ No access │　
       │ │　
       │ │　
       └───────────┘　

Note * 1

Store the following table in VRAM

-Command table

・ Character pattern table

・ Color look-up table

・ Gouraud shading table

Note * 2

080000 to 0BFFFFH has two frame buffers.

Only the drawing surface is accessible. The display surface is inaccessible.

● VRAM

• VRAM is 4Mbit DRAM.

• In VRAM, define a command table, a sprite character pattern table, a color lookup table, and a Gouraud shading table. Each piece of data can be anywhere in VRAM or nested. Specify the address for each and refer to it.

• The command table is always fetched from the beginning of VRAM (000000H).

• VRAM fetch
  Command table
  Gouraud shading table (only when using Gouraud shading)
  Color lookup table (only when using the lookup table method)
  Character pattern table (only when drawing sprites)

  It is repeated in the order of.

  If the command table fetch exceeds the VRAM end address (07FFFFH), it will be fetched back to the VRAM start address (000000H).

  Both byte access and word access are possible from the CPU.

  Read / write access from the syscon (system controller IC) to VRAM and parameter read and pattern read access from VDP1 are prioritized.

  VRAM access priority is always

  Syscon (system controller IC) ＞ Drawing

  The order is.

  Since the access is prioritized, the CPU operating clock may have a weight of about a dozen clocks depending on the timing. The CPU operating clock is 28MHz.

  To avoid interrupting drawing, access from the CPU when not drawing. Whether drawing is in progress is determined by polling the system register or using an interrupt signal. Also, use burst transfer to access VRAM and frame buffer in a short time.