★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 2 TV screen
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VDP2 User's Manual / Chapter 2 TV Screen

■ 2.5 External signal and scanning status

The registers that control the external signal include the external signal enable register, and the registers that display the scanning status of the TV include the screen status register, H counter register, and V counter register.

● External signal enable register

The external signal enable register controls the signal from outside the VDP2. A read-write 16-bit register located at address 180002H. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

EXTEN 180002H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
--- --- --- --- --- --- EXLTEN EXSYEN

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
--- --- --- --- --- --- DASEL EXBGEN

▲ External latch enable bit (EXLTEN), bit 9
Specifies the condition for latching the HV counter value to the HV counter register.

 EXLTEN
 Matters
 0
 Latch when reading an external signal enable register
 1
 Latch by external signal

The latched H counter value can be read in the H counter register, and the V counter value can be read in the V counter register.
Set to 1 when reading the H and V counter values by an external signal such as a raygun. Normally set to 0.

▲ External synchronization enable bit : EXSYNC enable bit (EXSYEN), bit 8
Controls the input of the external sync signal to the internal sync circuit.

 EXSYEN
 process
 0
 No external sync signal input
 1
 Input an external sync signal to synchronize the TV screen display with the outside

If you want to synchronize the screen display with other devices, set it to 1 and input the external synchronization signal. Normally, leave it at 0.

▲ Image display area select bit : Display area select bit (DASEL), bit 1
Specify the image display area. Valid only when the EXBGEN bit is 1.

 DASEL
 process
 0
 Display the image only in the setting display area
 1
 Display images in all standard display areas

When displaying in the entire standard display area, images from external screen data are displayed correctly in all. However, images other than the other (sprite, scroll screen, etc.) setting display area cannot be displayed correctly. Therefore, use a window to force other images to be transparent except for the setting display area.

▲ External screen enable bit : EXBG enable bit (EXBGEN), bit 0
Controls the input of external screen data.

 EXBGEN
 process
 0
 Do not enter external screen data
 1
 Enter external screen data

When inputting external screen data, that data will be the screen data of NBG1, so the settings for the external screen will be used for NBG1.
Table 2.2 shows the register bits for setting the external screen.

Table 2.2 Registers for external screen settings
 address
 Bit number
 Bit name
 180020H
 9
 N1TPON
 Transparent display enabled
 180028H
 13, 12
 N1CHCN1, N1CHCN0
 Number of character colors
 1800D0H
 8
 N1W0A
 W0 window area
 9
 N1W0E
 W0 window enabled
 Ten
 N1W1A
 W1 window area
 11
 N1W1E
 W1 window enabled
 12
 N1SWA
 SW window area
 13
 N1SWE
 SW window enabled
 15
 N1LOG
 Window logic
 1800E2H
 1
 N1SDEN
 Shadow enable
 1800E4H
 6-4
 N1CAOS2 to N1CAOS0
 Color RAM address offset
 1800E8H
 1
 N1LCEN
 Line color screen insertion enabled
 1800EAH
 3, 2
 N1SPRM1, N1SPRM0
 Special priority mode
 1800ECH
 1
 N1CCEN
 Color calculation enabled
 1800EEH
 3, 2
 N1SCCM, N1SCCM0
 Special color calculation mode
 1800F8H
 10-8
 N1PRIN2 to N1PRIN0
 Priority number
 180118H
 12-8
 N1CCRT4 to N1CCRT0
 Color calculation ratio
 180110H
 1
 N1COEN
 Color offset enable
 180112H
 1
 N1COSL
 Color offset select

● Screen status register

The screen status register displays information on the TV screen. A read-only 16-bit register located at address 180004H.

TVSTAT 180004H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
--- --- --- --- --- --- EXLTFG EXSYFG

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
--- --- --- --- VBLANK HBLANK ODD PAL

▲ External latch flag (EXLTFG), bit 9
Indicates whether the value of the HV counter has been latched into the HV counter register by an external signal. When the screen status register is read, it is cleared to 0.

 EXLTFG
 HV counter value status
 0
 Not yet latched in register
 1
 Latched to register

▲ External synchronization flag : External SYNC flag (EXSYFG), bit 8
Indicates whether the internal circuit has been synchronized by the external synchronization signal. When the screen status register is read, it is cleared to 0.

 EXSYFG
 External synchronization state
 0
 Out of sync
 1
 Internal circuit synchronized

▲ V blank flag : Vertical blank flag (VBLANK), bit 3
Indicates the vertical scanning status of the TV screen.

 VBLANK
 Vertical scanning state
 0
 Scanning during vertical display period
 1
 Scanning during vertical blanking interval (during VBLANK)

This bit is valid only when the TV screen display bit ( DISP ) in the TV screen mode register is 1. When the TV screen display bit ( DISP ) is 0, the V blank flag ( VBLANK ) is always 1.

▲ H blank flag : Horizontal blank flag (HBLANK), bit 2
Shows the horizontal scanning status of the TV screen.

 HBLANK
 Horizontal scanning state
 0
 Scanning during horizontal display period
 1
 Scanning during horizontal blanking interval (during HBLANK)

▲ Scanning field flag : Odd / even field flag (ODD), bit 1
Indicates the scanning status when the TV screen mode is interlaced mode.
In non-interlaced mode, it is always 1.

 ODD
 display
 0
 Scan during even field period
 1
 Scan during odd field period

▲ TV system flag : PAL / NTSC flag (PAL), bit 0
Shows the status of the TV system.

 PAL
 display
 0
 NTSC method
 1
 PAL method

● H counter register

The H counter register indicates the H counter value. A read-only 16-bit register located at address 180008H.

HCNT 180008H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
--- --- --- --- --- --- HCT9 HCT8

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
HCT7 HCT6 HCT5 HCT4 HCT3 HCT2 HCT1 HCT0

▲ H counter bit : H counter bit (HCT9 to HCT0), bits 9 to 0
A signal controlled by EXLTEN in the external signal enable register, which represents the value of the latched H counter. The bit configuration of this register changes depending on the graphic mode setting, as shown in Table 2.3.
In the case of normal graphics, the least significant bit HCT0 is invalid data for the H counter value. In the case of the dedicated normal graphic, the most significant bit HCT9 is invalid data for the H counter value.
In addition, the H counter value in the case of the dedicated high resolution graphic is a value in units of 2 dots because the most significant bit HCT9 is invalid data and there is no bit for H0.

Table 2.3 H counter register bit contents
 Graphic mode
 HCT9
 HCT8
 HCT7
 HCT6
 HCT5
 HCT4
 HCT3
 HCT2
 HCT1
 HCT0
 normal
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 invalid
 High resolution
 H9
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 Exclusive normal
 invalid
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1
 H0
 Exclusive high resolution
 invalid
 H9
 H8
 H7
 H6
 H5
 H4
 H3
 H2
 H1

● V counter register

The V-counter register indicates the V-counter value. A read-only 16-bit register located at address 18000AH.

VCNT 18000AH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
--- --- --- --- --- --- VCT9 VCT8

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCT7 VCT6 VCT5 VCT4 VCT3 VCT2 VCT1 VCT0

▲ V counter value bit : V counter bit (VCT9 to VCT0), bit 9 to 0
A signal controlled by EXLTEN in the external signal enable register, which represents the value of the latched V counter. The bit configuration of this register changes depending on the TV screen mode setting, as shown in Table 2.4. The V counter value for single-dense interlacing in normal and high resolution modes represents the V counter value in each of the even and odd fields. The V counter value in the case of double-dense interlacing in normal and high resolution modes is an odd field when VCT0 of the least significant bit is 0, an even field when VCT0 is 1, and VCT1 to VCT9 in each field. Represents the V counter value.

Table 2.4 V counter register bit contents
 TV screen mode
 (Interlaced)
 VCT9
 VCT8
 VCT7
 VCT6
 VCT5
 VCT4
 VCT3
 VCT2
 VCT1
 VCT0
 normal,
 High resolution (non-interlaced,
 (Single dense interlace)
 V9
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0
 normal,
 High resolution,
 (Double dense interlace)
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0
 0: odd number
 1: Even
 Dedicated monitor
 V9
 V8
 V7
 V6
 V5
 V4
 V3
 V2
 V1
 V0

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★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 2 TV screen
Copyright SEGA ENTERPRISES, LTD., 1997