Chapter 4 Scroll screen

■ 4.1 Screen display control

For the scroll screen, you can specify the screen that is not displayed by controlling the VRAM access for display for each screen. You can also specify for each screen whether to disable the dot color code (transparent code) that is the transparent dot of the screen to be displayed.

● Screen display enable register

The screen display enable register controls the screen display and the transparent code. A write-only 16-bit register located at address 18020H. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

BGON 180020H

15	14	13	12	11	Ten	09 09	08 08
---	---	---	R0TPON	N3TPON	N2TPON	N1TPON	N0TPON

07 07	06 06	05 05	04	03 03	02 02	01 01	00
---	---	R1ON	R0ON	N3ON	N2ON	N1ON	N0ON

　　　　　

Transparent enable bit : Transparent enable bit (N0TPON0, N1TPON, N2TPON, N3TPON, R0TPON)

Specifies whether to disable the transparent code. For the transparent code, refer to " Transparent Dot " in "4.3 Cell".

N0TPON	180020H	Bit 8	For NBG0 (or for RBG1)
N1TPON	180020H	Bit 9	For NBG1 (or for EXBG)
N2TPON	180020H	Bit 10	For NBG2
N3TPON	180020H	Bit 11	For NBG3
R0TPON	180020H	Bit 12	For RBG0

xxTPON	process
0	Enable transparent code (dots in transparent code will be transparent)
1	Disable transparent code (dots in transparent code are displayed according to their data values)

Note The bit name xx can be N0, N1, N2, N3, or R0.

　　　　　　

Screen display enable bit : On bit (N0ON, N1ON, N2ON, N3ON, R0ON, R1ON)

Specifies whether to display each scroll screen.

N0ON	180020H	Bit 0	For NBG0
N1ON	180020H	Bit 1	For NBG1
N2ON	180020H	Bit 2	For NBG2
N3ON	180020H	Bit 3	For NBG3
R0ON	180020H	Bit 4	For RBG0
R1ON	180020H	Bit 5	For RBG1

xxON	process
0	Cannot be displayed (VRAM access for display is not performed)
1	Can be displayed

Note The bit name xx can be N0, N1, N2, N3, R0, or R1.

If a screen access command with this bit set to 0 is set in the VRAM cycle pattern register, the access command is ignored and no VRAM access is made to display that screen.
Do not set R1ON to 1 when R0ON is 0.
If both R0ON and R1ON are set to 1, the normal scroll screen cannot be displayed. At this time, VRAM-B0 is fixed to RBG1's character pattern table RAM, and VRAM-B1 is fixed to RBG1's pattern name table RAM.
If a particular screen cannot be displayed due to register settings, set the bit on that screen to 0. For example, if both R0ON and R1ON are set to 1, set the N0ON, N1ON, N2ON, and N3ON bits to 0.
For the rotation scroll screen, refer to " 6.2 Rotation scroll screen display control ".