SEGA SATURN

How to use dual CPU

Ver1.1

February 10, 1995

table of contents

1. Introduction
2. Overview of dual CPU in Sega Saturn
3. About setting of development equipment for dual CPU
4. About programming using slave CPU
5. Communication between master CPU / slave CPU
6. About data transfer between master and slave
7. Program using slave CPU
8. Debugging method using one IBM-PC (including compatible machines)

■ 1. Introduction

This manual describes how to use two CPUs (SH2) installed in Sega Saturn. When Sega Saturn starts up, it runs only on the main CPU. To start the slave CPU, it is necessary to perform the procedure described in this manual.
This manual assumes that you have a general knowledge of Sega Saturn hardware and software. Please prepare and read the following manual.

• "SH7095 Hardware Manual"
• "SCU User's Manual" (HARDWARE MANUAL VOL.1)
• "System Program User's Manual"
• "CD Tools & Software Library Supplementary Documents"
• "SEGA SATURN Target Box User's Manual"

■ 2. Overview of dual CPU in Sega Saturn

This section provides an overview of dual CPUs in Sega Saturn.

● 2.1 Fully shared mode (memory sharing)

The Sega Saturn slave CPU shares all external devices with the master CPU. The program executed by the slave CPU and the reset vector acquired at the time of reset are completely the same as those of the master CPU.
However, since it is necessary to determine the master CPU and slave CPU in the BOOTROM and perform separate initialization for each CPU, the master / slave is determined inside the BOOTROM.
If the external access of the master CPU and the slave CPU conflicts, one of the CPUs will be kept waiting for access and the execution speed will decrease.

● 2.2 Communication by free running timer (FRT)

In Sega Saturn, the free running timer (FRT) input capture signal of the SH2 built-in module can be used as a means of communication between the master CPU and the slave CPU.
Specifically, if arbitrary data of 16-bit length is written to address 21000000H, an FRT input capture signal can be input to the slave CPU, and if arbitrary data of 16-bit length is written to address 218000000H, an FRT input capture signal can be input to the master CPU. increase.

● 2.3 Slave CPU interrupts

Unlike the master CPU, the slave CPU is not set to interrupt from the SCU. Therefore, interrupts are connected from the peripheral module (DCC) that controls this dual CPU.

(1) Interrupts used by the slave CPU

1. Interrupts that can be used by the slave CPU

You can use interrupts generated by 6 built-in peripheral modules including FRT.

2. H blank IN interrupt

The interrupt factor is IRL2 and the vector number is 65 (41H).

3. V blank IN interrupt


The interrupt factor is IRL6 and the vector number is 67 (43H).

The slave CPU does not have the SR mask limit that the master CPU does.
The SR mask must be used to disable interrupts.

(2) About H blank IN interrupt and V blank IN interrupt

In the slave CPU, both the H blank IN interrupt and the V blank IN interrupt are level signal interrupts that accept interrupts during the blank period.
For example, even if the V blank IN interrupt process is started and completed, the interrupt will be started again if it is still in the V blank period.
□ In order to call the interrupt function only once for each interrupt, it is necessary to take measures on the application side. The following two methods can be considered as specific methods.

1. How to wait for the end of a blank in an interrupt function

As a method of waiting for the end of the blank, the blank flag of the screen status register of VDP2 is monitored, and when the blank period ends, the interrupt function returns and the timer is set to the same length as the blank period at the beginning of the interrupt processing. A possible method is to return from the interrupt function after confirming that the set time has elapsed. The former accesses the external address (VDP2), which may reduce the performance on the master side.

2. How to operate the interrupt mask when returning

One possible method is to manipulate the interrupt mask saved on the stack so that the interrupt mask is not returned during the blank period even after returning from the interrupt function so that the same interrupt is not accepted.
A method using timer interrupts can be considered to realize this method, but as a precaution, other interrupts (internal interrupts) should be set to a higher level than H blank IN, V blank IN, and timer interrupts. is needed.

■ 3. About setting of development equipment for dual CPU

Explains how to set up and debug development equipment with dual CPUs.

● 3.1 How to develop dual CPU

When developing dual CPUs, connect the E7000 emulator or EVA board to the master side and slave side, respectively.

● 3.2 How to set up the E7000 emulator

When using the E7000 as the slave CPU, it is necessary to set the slave mode with the MODE command of the emulator.

    ★ Slave setting method: mode; c (RET)
	    E7000 MODE (MD5-0) = xx? 2E (RET)
	    MODE SET (C: CONFIGURATION / U: USER / M: MASTER-SALVE) = X? C (RET)
	    CONFIGURATION WRITE OK? (Y / N)? Y (RET)
    ★ Master setting E7000 MODE (MD5-0) = xx? 0E (RET)
  

● 3.3 How to set the EVA board

□ When using the EVA board for the slave CPU, the following settings are required. 1. Cancel reset □ Cancel the reset of the slave CPU with the emulator on the master CPU side. ★ How to release: m 2010001f; b (RET) 2010001f xx? 02 (RET) 20100020 xx? _ (RET) With the above settings, the EVA board on the slave CPU side will start. 2. Confirmation items □ Confirm that the EVA board on the slave CPU side is em ct = d. 3. Precautions □ When using an EVA board on the slave CPU side, the EVA board cannot be operated until the reset of the slave CPU is released.

● 3.4 About debugging environment

The following configurations are possible depending on the environment in which it is used.

1. Development on workstation

When developing on workstations (Sun SPARC series, HP9000 / 700 series), use the E7000 emulator on the master side and slave side, respectively. (Note: EVA board cannot be used) The software used can be operated with any combination of GUISH and LAN host system.

2. Development on IBM-PC compatibles

When developing with IBM-PC (including compatible machines), there are two methods, one is to use two PC compatibles and the other is to use one PC compatible. When using two units, it is possible to operate the master side and slave side at the same time. The software used can be any combination of GUISH and IPI.
However, in the case of one unit, the operation on the master side and the slave side is performed by switching the window. ( Chapter 8 explains the development method and restrictions on one IBM-PC)

■ 4. About programming using slave CPU

● 4.1 Program coexistence

Since the master CPU and slave CPU share all external devices, both can be freely executed anywhere in one executable file.
(When using the cache as the built-in RAM, the program placed in the built-in RAM is not shared.)

● 4.2 Stack variables, stacks, and global variables

Since the stack area is allocated individually (BOOT ROM setting) for the master CPU and slave CPU, any reentrant function can be executed at the same time. However, when both CPUs execute programs that rewrite static variables and global variables, it is necessary to pay attention to the execution order and simultaneous execution in each CPU.

● 4.3 Initialization of slave CPU

When the master CPU starts the slave CPU, the master CPU reads the BOOT ROM. After rewriting the post-initialization execution entry (SYS_SETSINT (0x94, EntryFunc);), the slave is reset in the SMPC I / F library. It is released by the slave SH2 ON function (PER_SMPC_SSH_ON).

* EntryFunc is a slave entry function

● 4.4 Initialization by BOOT ROM (vector, stack)

(1) The BOOT ROM initializes the slave CPU as follows.

-Vector base register (VBR) = address 6000400H

・ Stack pointer (SP) = 6001000H

-Interrupt initialization = FRT input capture interrupt enabled (64H, level 15)

(2) The vector table for the slave CPU on the work RAM is not changed by the ON / OFF operation of the slave SH2.

● 4.5 Clock change

When performing a clock change, the slave CPU shifts to the reset state by the SMPC. Therefore, after performing the clock change, the slave CPU is sent by the SMPC command (SSH_ON = 02H) or the slave SH2_ON function (PER_SMPC_SSH_ON) of the SMPC I / F library. , Needs to be restarted.

● 4.6 Precautions when using the slave CPU

The following contents cannot be executed on the slave CPU side.

・ Multiplayer call function cannot be used

-Programs that are premised on SCU interrupts cannot be used.

-Processing related to peripheral acquisition of SMPC I / F library is not possible.

■ 5. Communication between master CPU / slave CPU

This section describes the communication method between the master CPU and the slave CPU.

Reference: "SH7095 Hardware Manual" / 11. 16-bit free running timer

● 5.1 Communication from the master CPU to the slave CPU

Bidirectional communication means are required to operate the master CPU and slave CPU in a coordinated manner.

(1) FRT input capture interrupt

For the slave CPU, the FRT input capture interrupt is set by the initialization in the BOOT ROM. By registering an interrupt routine in 64H of the interrupt vector of the slave CPU in the application initialization routine, the processing when an interrupt occurs can be set from the master CPU.

→ The interrupt vector when registering from the master CPU is 164H.

Also, when this interrupt is generated from the master CPU, arbitrary 16-bit length data is written to address 21000000H. As a result, the slave CPU starts the interrupt processing registered in advance.

(2) Polling of FRT input capture flag

When the SH2CPU receives the FRT input capture flag, it sets the flag in the register inside the FRT unit, so there is also a method to monitor the change of this flag in the processing wait state (or synchronization wait state). This method takes less time to accept than when processing interrupts, so it is especially effective when there are many synchronizations and processing waits.
□ If you use this method, you must reconfigure the FRT input capture interrupt to disable it in your application's initialization routine.

→ TIMER: Set 01H in bytes at address FFFFFE10H

● 5.2 Communication from the slave CPU to the master CPU

(1) FRT input capture interrupt

For the master CPU, the FRT input capture interrupt is set by initialization in the BOOT ROM. By registering an interrupt routine in 64H of the interrupt vector of the master CPU in the application initialization routine, the processing when an interrupt occurs can be set from the master CPU.
Also, when this interrupt is generated from the slave CPU, arbitrary 16-bit length data is written to address 2180000H. As a result, the master CPU starts the interrupt processing registered in advance.

(2) Polling of FRT input capture flag

When the SH2CPU receives the FRT input capture flag, it sets the flag in the register inside the FRT unit, so there is also a method to monitor the change of this flag in the processing wait state (or synchronization wait state). This method takes less time to accept than when processing interrupts, so it is especially effective when there are many synchronizations and processing waits.
□ If you use this method, you must reconfigure the FRT input capture interrupt to disable it in your application's initialization routine.

■ 6. About data transfer between master and slave

The SH2 cache unit does not have a snoop function. When passing data between the master CPU and the slave CPU, the CPU that reads the data must read it by cache-through or after purging the cache of the target area.

Reference: "SH7095 Hardware Manual" / 8. Cache

● 6.1 Loading cache through

The cache-through is read from the address obtained by adding (logical sum) 2000000000H to the target address.

Details: "SCU User's Manual" / SCU Mapping

● 6.2 Cache initialization (purge)

There are two ways to purge the cache memory.

(1) Cache purge (all initialization)

Initialization is performed by writing "1" to the CP bit (4th bit) of the SH2 CCR (writing 10H in bytes to the address FFFFFE92H).
After performing this full initialization, it is necessary to write the value to CCR again and enable the cache.

Value to write

: In case of 4KB cache mode = 01H

: In case of 2KB cache + 2KB RAM = 09H

(2) Purging a specific line

This is done by writing "0" with 16-bit access to the address obtained by adding 40000000H to the target purge. This operation purges the 16-byte area including the target address.

■ 7. Program using slave CPU

Shows a program that uses a slave CPU. This section describes how to poll the FRT input capture flag.

● 7.1 Function that initializes / starts the slave CPU

Execute the function that initializes and starts the slave CPU on the master CPU.

	volatile Uint8 * SMPC_SF = (Uint8 *) 0x20100063; / * SMPC status flag * /
	volatile Uint8 * SMPC_COM = (Uint8 *) 0x2010001F; / * SMPC command register * /
	const Uint8 SMPC_SSHON = 0x02; / * SMPC slave SH on command * /
	const Uint8 SMPC_SSHOFF = 0x03; / * SMPC slave SH off command * /
	void InitSlaveCPU (void)
	{
		volatile Uint16 i;
		/ * Set the reset state of SlaveSH * /

● 7.2 Entry function from main CPU to slave CPU

How to poll the FRT input capture flag

● 7.3 Function execution request from master CPU to slave CPU

■ 8. Debugging method using one IBM-PC (including compatible machines)

There are the following two methods for debugging dual CPUs by connecting an E7000 PC and EVA board with one IBM-PC (including compatible machines).

● 8.1 Setting and operation method when using only IPI

Open two DOS prompts of MS-Windows and run IPI on each window. In explaining the setting procedure, it is assumed that the E7000 is connected to the master side and the EVA board is connected to the slave side.

Connection example

	Tools used	soft	IBM interface board
Master side	E7000PC	IPI.EXE	D000: 0000H IRQ11
Slave side	EVA board	IPI.EXE	D400: 0000H IRQ12

★ The above settings are based on the assumption that they will not collide with other expansion board settings.

(2) CONFIG.SYS settings

If you have installed a virtual expanded memory driver in CONFIG.SYS, you need to change its settings. For the setting method, refer to "IBM-PC Interface User's Manual / p6 to p7".
In the connection example, if the master board and slave board memory address ranges (D0000H to D3FFFH and D4000H to D7FFFH) are set under the control of the virtual EMS driver and the base address of the EMS page frame is set to E0000H,

DEVICE = C: \ WINDOWS \ EMM386.EXE RAM /X=D000-D7FF FRAME = E000

(4) Setting environment variables

Set the environment variables used by the slave board on the master board. It is convenient to define this environment variable in AUTOEXEC.BAT. Be sure to set the mounting addresses of the master board and slave board in the environment variables. If not set, two IPIs will use the master board at the same time.

In the connection example,

	   SET SYS1 = C: \ SYS1,1B, D0 It is necessary to install the E7000PC system in the environment variable of IPI on the master side → \ SYS1.               				   
	   SET SYS2 = C: \ SYS2,1B, D4 Slave side IPI environment variables

Note: If you want to use E7000 on the slave side, you need to install the E7000PC system program in \ SYS2.

(1) Setting the mounting address of the PC I / F board

The mounting address of the PC I / F connected by GUISH must be set higher than the mounting address of the PC I / F board connected by IPI.
In the connection example, GUISH is used on the master side, so D000: 0000H, which is higher than the implementation address D400: 0000H on the slave side, is set.

(2) CONFIG.SYS settings

If you have installed a virtual expanded memory driver in CONFIG.SYS, you need to change its settings. For the setting method, refer to "IBM-PC Interface User's Manual / p6 to p7".
In the connection example, if the master board and slave board memory address ranges (D0000H to D3FFFH and D4000H to D7FFFH) are set under the control of the virtual EMS driver and the base address of the EMS page frame is set to E0000H,

DEVICE = C: \ WINDOWS \ EMM386.EXE RAM /X=D000-D7FF FRAME = E000

(4) Setting environment variables

Set the environment variables used by GUISH (master side) and IPI (slave side). It is convenient to define this environment variable in AUTOEXEC.BAT in advance. Be sure to set the mounting address with the slave board in the environment variable used by IPI.
If not set, GUISH and IPI will use the master board at the same time.

In the connection example, the settings are as follows.

---------------------------------------------

SET GUISH PATH = C: \ GUISH GUISH environment variable SET E7000SYS = C: \ SYS2, IB, D4 IPI environment variable -------------- --------------------

(5) How to start

1. Start the master side (GUISH) Click the E7000PC icon in the MS-Windows GUISH group.
   GUISH starts and connects to the E7000 PC.
   The E7000 monitor menu will be displayed in the GUISH command area. Enter "S" or "R" to load the E7000PC system program. When the E7000PC prompt: is displayed, start the slave side next.

2. Slave side (IPI) startup
   After starting the DOS prompt in the main group of MS-Windows, start IPI as shown below and connect to the E7000PC.

   ---------------------------------------------
   
   C: \> IPI (RET)
   
   ---------------------------------------------
   

   In the E7000 monitor menu, enter "S" or "R" to load the system program of the E7000PC.