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SCU User's Manual / Chapter 1 Overview

■ 1.3 SCU register map

Figure 1.6 shows the register map of the SCU. The SCU register is assigned to the highest address in the SCU mapping area, and an area of 208 bytes is secured as shown in Fig. 1.3. In addition, the map of each register area is shown below.

Figure 1.6 SCU register map

25FE0000H
 Level-0 DMA set register 32byte

25FE0020H
 Level-1 DMA set register 32byte

25FE0040H
 Level-2 DMA set register 32byte
25FE0060H
 unused 16byte
25FE0070H
 unused 16byte
25FE0080H DSP program control port 4byte
25FE0084H DSP program RAM data port 4byte
25FE0088H DSP data RAM address port 4byte
25FE008CH DSP data RAM data port 4byte
25FE0090H Timer 0 compare register 4byte
25FE0094H Timer 1 set data register 4byte
25FE0998H Timer 1 mode register 4byte
25FE009CH unused 4byte
25FE00A0H Interrupt mask register 4byte
25FE00A4H Interrupt status register 4byte
25FE00A8H A-Bus interrupt acknowledge 4byte
25FE00ACH unused 4byte
25FE00B0H
 A-Bus setting register 8byte
25FE00B8H A-Bus refresh register 4byte
25FE00BCH
 unused 8byte
25FE00C4H SCU SDRAM selection register 4byte
25FE00C8H SCU version register 4byte
25FE00CCH unused 4byte

caution
 -Access (read / write) to unused areas is prohibited.
-Be sure to use the cache-through address to access the SCU register.

◆ Level 2-0 DMA set register

Figure 1.7 shows a map of the Level 2-0 DMA set registers. This register contains the parameters required for DMA transfer. As shown in the SCU register map (Fig. 1.6), there are three types of DMA levels (level 0 to level 2), so the addresses in Fig. 1.7 are represented by relative addresses.

Figure 1.7 Level 2-0 DMA set register map
bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 + 00H − Read address (in bytes) (R / W)
 + 04H − Write address (in bytes) (R / W)
 + 08H Write address (in bytes) (R)
 + 0CH − 1 − 2
 + 10H − 3 − 4
 + 14H − 5 − 6 − 7 − 8
 + 18H −
 + 1CH −
 In the figure
  1.  Read address addition value
  2.  Write address addition value
  3.  DMA allow bit (= 0: Disable / = 1: Enable)
  4.  DMA start bit
  5.  DMA mode bits
  6.  Read address update bit (= 0: hold / = 1: update
  7.  Write address update bit (= 0: hold / = 1: update)
  8.  DMA activation factor selection bit
 ◆ DSP program control port
 Figure 1.10 shows a map of DSP program control ports. DSP control register. It also stores the DSP operation start address and end address.
 Figure 1.10 DSP program control portmap
 bit
 31
 26
 twenty four
 twenty three
 16
 15 
 7
 0
 25FE0080H − 1 2 − 3 4 5 6 7 8 9 Ten 11 − Program RAM
 address
 In the figure
  1.  Release pause at EX = 1 (= 0: non-execution / = 1: execution)
  2.  Pause execution at EX = 1 (= 0: non-execution / = 1: execution)
  3.  D0 bus use DMA transfer execution flag
  4.  Sign flag
  5.  Zero flag
  6.  Carry flag
  7.  Overflow hula
  8.  Program end interrupt hula
  9.  Program step execution control bit (= 0: non-execution / = 1: execution
  10.  Program execution control (= 0: / = 1 :)
  11.  Program counter load permission (= 0: non-execution / = 1: execution)
 ◆ DSP program RAM data port
 Figure 1.11 shows a map of the DSP program RAM data ports. It is used as an intermediary when transferring program data from the CPU to the DSP.
 Figure 1.11 DSP Program RAM Data Port Map
 bit
 31
 26
 twenty four
 twenty three
 16
 15 
 7
 0
 25FE0084H Program RAM data (W)
 ◆ DSP data RAM address port
 Figure 1.12 shows a map of DSP data RAM address ports. Specifies the data RAM address when accessing the data RAM inside the DSP from the CPU.
 Figure 1.12 DSP data RAM address portmap
 bit
 31
 26
 twenty four
 twenty three
 16
 15 
 7
 0
 25FE0088H − Data RAM
 address
 ◆ DSP data RAM data port
 Figure 1.13 shows a map of DSP data RAM data ports. DSP Data Contains the contents of the address indicated by the RAM address port. When writing from the CPU, it is stored in the DSP data RAM, and when reading from the CPU, the data in the DSP's internal RAM can be retrieved.
 Figure 1.13 DSP data RAM data port map
 bit
 31
 26
 twenty four
 twenty three
 16
 15 
 7
 0
 25FE008CH Data RAM data (W)
 ◆ Timer 0 compare register
 Figure 1.14 shows a map of the timer 0 compare register. Timer 0 synchronizes with the V-blank-IN interrupt (see Section 2.2, Interrupt Control) and generates an interrupt. The operation is described in Section 2.2, and the contents of the registers are described in Chapter 3.
 Figure 1.14 Timer 0 compare register map
 bit
 31 
 9 
 0
 25FE0090H − Counter value
 ◆ Timer 1 set data register
 Figure 1.15 shows a map of the timer 1 set data register. Timer 1 is set with an H-blank-IN interrupt (see Section 2.2, Interrupt Control), decremented in a 7MHz cycle, and an interrupt occurs when the data reaches zero. The operation is in Section 2.2, and the contents of the registers are described in Chapter 3.
 Figure 1.15 Timer 1 set data register map
 bit
 31 
 8 
 0
 25FE0094H − Set data
 ◆ Timer 1 mode register
 Figure 1.16 shows a map of the timer 1 mode registers. This register specifies when timer 1 should be generated. The operation is in Section 2.2, and the contents of the registers are described in Chapter 3.
 Figure 1.16 Timer 1 mode register map
 bit
 31 
 8 
 0
 25FE0098H − 1 − 2
 In the figure,
 1. Timer 1 mode bit
 = 0: Occurs every line
 = 1: Only the line specified by timer 0 occurs
 2. Timer operation enable bit
 = 0: Timer operation OFF
 = 1: Timer operation ON
 ◆ Interrupt mask register
 Figure 1.17 shows a map of the interrupt mask registers. When this bit is 0, the interrupt is not masked and an interrupt is generated as requested. Also, when it is 1, the interrupt is masked, so no interrupt is generated. The details from bit0 (number 15 in the figure) to bit13 (number 2 in the figure) are explained in detail in Chapter 3.
 Figure 1.17 Interrupt mask register map
 bit
 31 
 15 
 0
 25FE00A0H − 1 − 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15
 In the figure,
 1. A-Bus interrupt bit
 2 to 15. Interrupt mask bit
 ◆ Interrupt status register
 Figure 1.18 shows a map of the interrupt status register. This register is a readable / writable register. At the time of reading, if the bit data is 0, it means that no interrupt has occurred, and if it is 1, it means that an interrupt has occurred. When writing, writing 0 resets the interrupt, and writing 1 retains the current interrupt state. The details of this register are described in detail in Chapter 3.
 Figure 1.18 Interrupt status register map
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE00A4 1 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15 16 − 17 18 19 20 twenty one twenty two twenty three twenty four twenty five 26 27 28 29 30
 In the figure,
 1-30. Interrupt status bits
 ◆ A-Bus interrupt acknowledge register
 Figure 1.19 shows a map of the A-Bus interrupt acknowledge. This bit is a readable and writable bit and has different meanings when reading and writing. Details are explained in Chapter 3.
 Figure 1.19 A-Bus Interrupt Acknowledgment Register Map
 bit
 31 
 0
 25FE00A8H − 1
 In the figure,
 1. READ: A-Bus interrupt acknowledge enabled bit (= 0: disabled / = 1: enabled)
 WRITE: A-Bus interrupt Acknowledgment valid bit (= 0: disabled / = 1: enabled)
 ◆ A-Bus setting register
 Figure 1.20 shows a map of the A-Bus configuration registers. Each read-ahead valid bit, precharge insert bit, and external weight valid bit is invalid at 0 and valid at 1. Details are explained in Chapter 3.
 Figure 1.20 A-Bus configuration register map
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE00B0 − 2 3 4 5 6 7 8 9 Ten 11 12 13 14 − 15 − 17 18 19 20 twenty one twenty two twenty three twenty four twenty five 26 27 28 29 − 30
 25FE00B4 − 32 33 34 −  − − − − − − − 35 36 − 37 38 39 40 41 42 43 44 45 46 47 − 49 50 51 − 52
 In the figure
  2. CS0 space, precharge insertion bit after write　
  3.CS0 space, precharge insertion bit after read　
  4. CS0 space, external weight valid bit　
 5 to 8. CS0 space, burst cycle weight number setting bit　
 9 to 12.CS0 space, normal cycle weight number setting bit　
13-14. CS0 space, burst length setting bit　
  15.CS0 space, bus size setting bit　

  17. CS1 space, precharge insertion bit after write　
  18. CS1 space, precharge insertion bit after read　
  19. CS1 space, external weight valid bit　
20-23. CS1 space, burst cycle weight number setting bit　
24-27.CS1 space, normal cycle weight number setting bit　
28-29. CS1 space, burst length setting bit　
  30.CS1 space, bus size setting bit　

  32. CS2 space, precharge insertion bit after write　
  33. CS2 space, precharge insertion bit after read　
  34. CS2 space, external weight valid bit　
35-36.CS2 space, burst length setting bit　
  37. CS2 space, bus size setting bit　

  39. Spare space, precharge insertion bit after write　
  40. Spare space, precharge insertion bit after read　
  41. Spare space, external weight significant bit　
42 to 45. Spare space, burst cycle weight number setting bit　
46 to 49. Spare space, normal cycle weight number setting bit　
50-51. Spare space, burst length setting bit　
  52. Spare space, bus size setting bit　


◆ A-Bus refresh register
 Figure 1.21 shows a map of the A-Bus refresh register. Make settings for refreshing A-Bus.
 Figure 1.21 A-Bus refresh register map
 bit
 31 
 4
 0
 25FE00B8H − 1 2 3 4 5
 In the figure,
 1. A-Bus refresh output valid bit (= 0: invalid / = 1: valid)
 2 to 5. A-Bus refresh weight number setting bit
 ◆ SCU SDRAM selection register
 Figure 1.22 shows a map of the SCU SDRAM select register.
 Figure 1.22 SCU SDRAM selection register map
 bit
 31 
 0
 25FE00C4H − 1
 In the figure,
 1. SDRAM selection bit
 ◆ SCU version register
 Figure 1.23 shows a map of the SCU version registers.
 Figure 1.23 SCU version register map
 bit
 31 
 3
 0
 25FE00C8H − 1 2 3 4
 In the figure,
 1-4. Version number
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