Chapter 2 Operation explanation

■ 2.1 DMA transfer

◆ Basic operation of DMA

Figure 2.1 shows the basic operation of DMA. This DMA is basically longword access via the buffer of the DMA controller, but if the start address and end address are not on the longword boundary, read / write in byte units and execute DMA transfer. I can.
Figure 2.1 shows an example of performing DMA transfer from the transfer source address 1H to 50H to the transfer destination address 6H to 55H. At the transfer source, the longword boundary is 4H, so 1H to 3H is read in byte units. increase. On the other hand, at the transfer destination, the longword boundary is 8H, so the first 2 bytes of the read data are written to 6H to 7H in byte units. Furthermore, the transfer source end address is 50H, but the longword boundary is up to 4FH, so 50H data is read in bytes. On the other hand, the transfer destination end address is 55H, but the longword boundary is up to 53H, so the last 2 bytes read are written to 54H to 55H in byte units.

Figure 2.1 Basic operation of DMA transfer

There are two ways to start the SCU's DMA transfer control.

1. DMA startup from main CPU
2. DMA activation from DSP

Figure 2.2 shows the DMA transferable area when booting from the main CPU, and Figure 2.3 shows the DMA transferable area when booting from the DSP.

Figure 2.2 DMA transferable area when booted from the main CPU

Figure 2.3 DMA transferable area when booted from DSP

	Precautions regarding DMA

● Write protection to A-Bus by SCU-DMA

Writing to A-Bus by SCU-DMA cannot be used.

● Write protection by SCU-DMA from VDP2 area

Writing by SCU-DMA from the VDP2 area cannot be used.

● SCU-DMA cannot be used for WORKRAM-L

Only WORKRAM-HI (SDRAM: 1Mbyte) can use SCU-DMA with WORKRRAM.

● A-Bus ← → B-Bus DMA access prohibited from CPU running to A-Bub and B-Bus

Access to A-Bus and B-Bus from the CPU is prohibited during DMA operation from A-Bus to B-Bus and from B-Bus to A-Bus. This is because during the weighting, the SDRAM may not be refreshed and may hang.

● Waiting for A-Bus ← → B-Bus SCU-DMA to start when writing to A-Bus and B-Bus by CPU

CPU write processing to A-Bus and B-Bus has priority over starting SCU-DMA of A-Bus and B-Bus.
For example, when continuous write is executed on the CPU for VDP1 (B-Bus), continuous write ends even if SCU-DMA is started from A-Bus to VDP2 (B-Bus). SCU-DMA will not start until you do.
However, CPU access to A-Bus and B-Bus is waited for while SCU-DMA is running.

● 2 channels can be used simultaneously for DMA

Up to 2 channels can be used simultaneously with guaranteed DMA priority.
If 3 channels are used at the same time, the priority will be ignored. (DSP DMA instructions are also counted as one channel)

● Do not start DMA level 2 while DMA level 1 is running

Starting DMA level 2 while DMA is running at level 1 may cause a malfunction.
As a countermeasure, do not start DMA level 2 while starting with DMA level 1.

● Write protection for the corresponding level while DMA is running

The contents of the DMA mode, address update, activation factor selection register, and addition value register must not be rewritten during DMA activation at that level.
It hangs when rewritten.

● Prohibitions of SCU-DMA indirect mode

Prohibits the use of SCU-DMA indirect mode for reading from the CD buffer.
Perform SCU-DMA direct mode, CPU-DMA or software transfer.
For transfers that use the A-BUS space as the source as well as the CD buffer, only "4 byte addition" can be specified for the source read address addition value , and the setting of "do not add" is prohibited.
There is no such limitation for SCU-DMA direct mode.