★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
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VDP2 User's Manual / Chapter 3 RAM

■ 3.2 VRAM bank split

VDP2 can access four banks of VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1 at the same time by dividing VRAM-A and VRAM-B into two. Therefore, more image data can be obtained at one time than when not divided into two, and the number of scroll screens that can be displayed at the same time can be increased, or screens with a large number of colors can be displayed. However, there are restrictions on specifying VRAM read / write access by the CPU during the display period. Therefore, if you want to perform a lot of read / write access by the CPU during the display period, you can perform efficient access by dividing the VRAM into two instead of dividing it into two in the normal case.

● RAM control register

The RAM control register specifies the banking of VRAM, the purpose of VRAM on the rotating scroll screen, and the color RAM mode. A read-write 16-bit register located at address 18000EH. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

RAMCTL 18000EH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
CRKTE --- CRMD1 CRMD0 --- --- VRBMD VRAMD

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
RDBSB11 RDBSB10 RDBSB01 RDBSB00 RDBSA11 RDBSA10 RDBSA01 RDBSA00

Color RAM coefficient table bit: Color RAM coefficient table enable bit ( CRKTE), bit 15
See 6.4 Coefficient Table Control.

Color RAM mode bits : Color RAM mode bits (CRMD1, CRMD0), bits 13, 12
Refer to " 3.4 Color RAM Mode".

When the CRKTE bit is set to 1, set the color RAM mode to mode 1. At that time, the latter half of the color RAM (100800H to 100FFFH) is used for the coefficient table data, so the color data cannot be stored.

VRAM mode bit : VRAM mode bit (VRBMD, VRAMD)
Controls VRAM banking.

 VRAMD
 18000EH
 Bit 8
 For VRAM-A
 VRBMD
 18000EH
 Bit 9
 For VRAM-B

 VRxMD
 process
 0
 Do not split into two banks
 1
 Divide into two banks
Note The x in the bit name can be A or B.

Rotation data bank specification bit : RBG0 data bank select bit (RDBSA00 to RDBSB11), bits 7 to 0
Refer to " 6.2 Rotation Scroll Screen Display Control".
When the CRKTE bit is set to 1, do not specify that 4 banks of VRAM should be used as RAM for coefficient table data.

● Storage location of pattern name data

The pattern name data storage location of the scroll surface has the following restrictions regardless of the normal scroll surface or the rotary scroll surface.
Table 3.2 below shows the restrictions on VRAM mode bits and pattern name data storage locations.
There are no restrictions on the storage location of character pattern data or bitmap pattern data.

  1. When neither VRAM-A nor VRAM-B is divided into two
    Can only be stored in either VRAM-A or VRAM-B

  2. When dividing only VRAM-A into two
    a) When storing in VRAM-B, it may be stored in VRAM-A1.
    b) When not stored in VRAM-B, it may be stored in either VRAM-A0 or A1.

  3. When dividing only VRAM-B into two
    a) When storing in VRAM-A, it may be stored in VRAM-B1.
    b) When not stored in VRAM-A, it may be stored in either VRAM-B0 or B1.

  4. When dividing both VRAM-A and VRAM-B into two
    It can only be stored in either VRAM-A0 or VRAM-B0 and either VRAM-A1 or VRAM-B1.

Table 3.2 Restrictions on pattern name data storage location
 VRAM mode bit setting
 Pattern name data storage location
VRAMD VRBMD VRAM-A VRAM-B
VRAM-A0 VRAM-A1 VRAM-B0 VRAM-B1
0 0 ○ ×
× ○
1 0 × ○ ○
○ ○ ×
0 1 ○ × ○
× ○ ○
1 1 ○ ○ × ×
○ × × ○
× ○ ○ ×
× × ○ ○
○: Can be stored
×: Cannot be stored
[Note] If there are multiple locations that can be stored, it is not necessary to store them in all.

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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
Copyright SEGA ENTERPRISES, LTD., 1997