★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
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VDP2 User's Manual / Chapter 3 RAM / ■ 3.3 How to access VRAM during the display period
● VRAM cycle pattern register specification procedure
- The procedure for specifying a VRAM cycle pattern in a register is as follows.
- Determine the TV screen mode.
- Decide if you want to split the VRAM in two.
- Determine the number of character colors and reduction settings for the scroll screen to be displayed.
Also, decide whether to use the vertical cell scroll function. - Determine the VRAM bank that stores the image data (pattern name data, character pattern data, bitmap pattern data) required for each scroll screen.
When using the vertical cell scroll function, also determine the bank of VRAM that stores the vertical cell scroll table data. - Decide whether to perform read / write access by the CPU.
- Specify the access command in the VRAM cycle pattern register so as to comply with the specification restrictions of each access timing.
- Figure 3.8 shows an example of specifying the VRAM cycle pattern register.
- Figure 3.8 VRAM cycle pattern specification example
- <Conditions>
- Set TV screen mode to normal mode
- Divide both VRAM-A and VRAM-B
- Set the scroll screen as shown in the table below.
| screen name | Number of character colors | Reduction setting | Vertical cell scroll function |
|---|
| NBG0 | 256 colors | 1/2 times | do not use |
| NBG1 | 256 colors | 1x | use |
| NBG3 | 16 colors | 1x | --- |
- The bank that stores each data of the scroll screen is as shown in the table below.
| screen name | Pattern name | Character pattern | Vertical cell scroll table |
|---|
| NBG0 | A0 | B0, B1 | --- |
| NBG1 | A0, A1 | B0, B1 | A0 |
| NBG3 | A1 | A1, B0 | --- |
- A0: VRAM-A0 A1: VRAM-A1
- B0: VRAM-B0 B1: VRAM-B1
- Allow CPU read / write access to VRAM-A
- <VRAM cycle pattern register>
| T0 | T1 | T2 | T3 | T4 | T5 | T6 | T7 |
|---|
For VRAM-A0
(Or for VRAM-A) | N1CE | N0PN | N1PN | N0PN | NA | CPU | CPU | NA |
|---|
| For VRAM-A1 | N3CE | NA | N1PN | NA | NA | CPU | CPU | N3CG |
|---|
For VRAM-B0
(Or for VRAM-B) | N0CG | N0CG | N1CG | N1CG | NA | N0CG | N0CG | N3CG |
|---|
| For VRAM-B1 | N0CG | N0CG | N1CG | N1CG | NA | N0CG | N0CG | NA |
|---|
- N1 = NBG1 N2 = NBG2 N3 = NBG3
- PN = pattern name data read
- CG = character pattern data read
- CE = Vertical cell scroll table data read
- CPU = CPU read / write
- NA = do not access
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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
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