★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 3 RAM
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VDP2 User's Manual / Chapter 3 RAM / ■ 3.3 How to access VRAM during the display period

● VRAM cycle pattern register

The VRAM cycle pattern register controls VRAM access during the display period. This is a write-only 16-bit register located at addresses 180010H to 18001EH. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

CYCA0L 180010H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP0A03 VCP0A02 VCP0A01 VCP0A00 VCP1A03 VCP1A02 VCP1A01 VCP1A00

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP2A03 VCP2A02 VCP2A01 VCP2A00 VCP3A03 VCP3A02 VCP3A01 VCP3A00

CYCA0U 180012H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP4A03 VCP4A02 VCP4A01 VCP4A00 VCP5A03 VCP5A02 VCP5A01 VCP5A00

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP6A03 VCP6A02 VCP6A01 VCP6A00 VCP7A03 VCP7A02 VCP7A01 VCP7A00

CYCA1L 180014H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP0A13 VCP0A12 VCP0A11 VCP0A10 VCP1A13 VCP1A12 VCP1A11 VCP1A10

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP2A13 VCP2A12 VCP2A11 VCP2A10 VCP3A13 VCP3A12 VCP3A11 VCP3A10

CYCA1U 180016H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP4A13 VCP4A12 VCP4A11 VCP4A10 VCP5A13 VCP5A12 VCP5A11 VCP5A10

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP6A13 VCP6A12 VCP6A11 VCP6A10 VCP7A13 VCP7A12 VCP7A11 VCP7A10

CYCB0L 180018H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP0B03 VCP0B02 VCP0B01 VCP0B00 VCP1B03 VCP1B02 VCP1B01 VCP1B00

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP2B03 VCP2B02 VCP2B01 VCP2B00 VCP3B03 VCP3B02 VCP3B01 VCP3B00

CYCB0U 18001AH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP4B03 VCP4B02 VCP4B01 VCP4B00 VCP5B03 VCP5B02 VCP5B01 VCP5B00

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP6B03 VCP6B02 VCP6B01 VCP6B00 VCP7B03 VCP7B02 VCP7B01 VCP7B00

CYCB1L 18001CH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP0B13 VCP0B12 VCP0B11 VCP0B10 VCP1B13 VCP1B12 VCP1B11 VCP1B10

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP2B13 VCP2B12 VCP2B11 VCP2B10 VCP3B13 VCP3B12 VCP3B11 VCP3B10

CYCB1U 18001EH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
VCP4B13 VCP4B12 VCP4B11 VCP4B10 VCP5B13 VCP5B12 VCP5B11 VCP5B10

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
VCP6B13 VCP6B12 VCP6B11 VCP6B10 VCP7B13 VCP7B12 VCP7B11 VCP7B10

Table 3.5 shows the access commands corresponding to the contents of VRAM access performed during one cycle.

Table 3.5 Access commands
 Access command value
 VRAM access content
 VCPnxx3
 VCPnxx2
 VCPnxx1
 VCPnxx0
 0
 0
 0
 0
 Pattern name data read for NBG0
 0
 0
 0
 1
 Pattern name data read for NBG1
 0
 0
 1
 0
 Pattern name data read for NBG2
 0
 0
 1
 1
 Pattern name data read for NBG3
 0
 1
 0
 0
 Character pattern data read for NBG0
 0
 1
 0
 1
 Character pattern data read for NBG1
 0
 1
 1
 0
 Character pattern data read for NBG2
 0
 1
 1
 1
 Character pattern data read for NBG3
 1
 0
 0
 0
 Setting prohibited
 1
 0
 0
 1
 Setting prohibited
 1
 0
 1
 0
 Setting prohibited
 1
 0
 1
 1
 Setting prohibited
 1
 1
 0
 0
 Vertical cell scroll table data read for NBG0
 1
 1
 0
 1
 Vertical cell scroll table data read for NBG1
 1
 1
 1
 0
 CPU read / write
 1
 1
 1
 1
 Do not access
[note]
n: 0 to 7 (corresponds to access timing T0 to T7)
xx: A0, A1, B0, B1 (corresponding to VRAM-A0, VRAM-A1, VRAM-B0, VRAM-B1)

VRAM cycle pattern bit (for VRAM-A0): VRAM cycle pattern bit
(VCP0A00 to VCP0A03, VCP1A00 to VCP1A03, VCP2A00 to VCP2A03, VCP3A00 to VCP3A03, VCP4A00 to VCP4A03, VCP5A00 to VCP5A03, VCP6A00 to VCP6A03, VCP7A00 to VCP7A03)
VRAM-A0 (or VRAM-A) timing Set the access command for VRAM access to be performed from T0 to T7.

 VCP0A00 to VCP0A03
 180010H
 Bits 12-15
 For VRAM-A0 (or VRAM-A) timing T0
 VCP1A00 to VCP1A03
 180010H
 Bits 8-11
 For VRAM-A0 (or VRAM-A) timing T1
 VCP2A00 to VCP2A03
 180010H
 Bits 4-7
 For VRAM-A0 (or VRAM-A) timing T2
 VCP3A00 to VCP3A03
 180010H
 Bits 0-3
 For VRAM-A0 (or VRAM-A) Timing T3
 VCP4A00 to VCP4A03
 180012H
 Bits 12-15
 For VRAM-A0 (or VRAM-A) Timing T4
 VCP5A00 to VCP5A03
 180012H
 Bits 8-11
 For VRAM-A0 (or VRAM-A) Timing T5
 VCP6A00 to VCP6A03
 180012H
 Bits 4-7
 For VRAM-A0 (or VRAM-A) Timing T6
 VCP7A00 to VCP7A03
 180012H
 Bits 0-3
 For VRAM-A0 (or VRAM-A) Timing T7

VRAM cycle pattern bit (for VRAM-A1): VRAM cycle pattern bit
(VCP0A10 to VCP0A13, VCP1A10 to VCP1A13, VCP2A10 to VCP2A13, VCP3A10 to VCP3A13, VCP4A10 to VCP4A13, VCP5A10 to VCP5A13, VCP6A10 to VCP6A13, VCP7A10 to VCP7A13)
VRAM-A1 Timing Set the access command for VRAM access to be performed from T0 to T7.

 VCP0A10 to VCP0A13
 180014H
 Bits 12-15
 For VRAM-A1 timing T0
 VCP1A10 to VCP1A13
 180014H
 Bits 8-11
 For VRAM-A1 timing T1
 VCP2A10 to VCP2A13
 180014H
 Bits 4-7
 For VRAM-A1 timing T2
 VCP3A10 to VCP3A13
 180014H
 Bits 0-3
 For VRAM-A1 timing T3
 VCP4A10 to VCP4A13
 180016H
 Bits 12-15
 For VRAM-A1 timing T4
 VCP5A10 to VCP5A13
 180016H
 Bits 8-11
 For VRAM-A1 timing T5
 VCP6A10 to VCP6A13
 180016H
 Bits 4-7
 For VRAM-A1 timing T6
 VCP7A10 to VCP7A13
 180016H
 Bits 0-3
 For VRAM-A1 timing T7

If you do not split VRAM in two, the value of this register is ignored.

VRAM cycle pattern bit (for VRAM-B0) bit: VRAM cycle pattern bit

(VCP0B00 to VCP0B03, VCP1B00 to VCP1B03, VCP2B00 to VCP2B03, VCP3B00 to VCP3B03, VCP4B00 to VCP4B03, VCP5B00 to VCP5B03, VCP6B00 to VCP6B03, VCP7B00 to VCP7B03)
VRAM-B0 (or VRAM-B) timing Set the access command for VRAM access to be performed from T0 to T7.

 VCP0B00 to VCP0B03
 180018H
 Bits 12-15
 For VRAM-B0 (or VRAM-B) timing T0
 VCP1B00 to VCP1B03
 180018H
 Bits 8-11
 For VRAM-B0 (or VRAM-B) timing T1
 VCP2B00 to VCP2B03
 180018H
 Bits 4-7
 For VRAM-B0 (or VRAM-B) timing T2
 VCP3B00 to VCP3B03
 180018H
 Bits 0-3
 For VRAM-B0 (or VRAM-B) Timing T3
 VCP4B00 to VCP4B03
 18001AH
 Bits 12-15
 For VRAM-B0 (or VRAM-B) Timing T4
 VCP5B00 to VCP5B03
 18001AH
 Bits 8-11
 For VRAM-B0 (or VRAM-B) Timing T5
 VCP6B00 to VCP6B03
 18001AH
 Bits 4-7
 For VRAM-B0 (or VRAM-B) Timing T6
 VCP7B00 to VCP7B03
 18001AH
 Bits 0-3
 For VRAM-B0 (or VRAM-B) Timing T7

VRAM cycle pattern bit (for VRAM-B1): VRAM cycle pattern bit
(VCP0B10 to VCP0B13, VCP1B10 to VCP1B13, VCP2B10 to VCP2B13, VCP3B10 to VCP3B13, VCP4B10 to VCP4B13, VCP5B10 to VCP5B13, VCP6B10 to VCP6B13, VCP7B10 to VCP7B13)
VRAM-B1 Timing Set the access command for VRAM access to be performed from T0 to T7.

 VCP0B10 to VCP0B13
 18001CH
 Bits 12-15
 For VRAM-B1 timing T0
 VCP1B10 to VCP1B13
 18001CH
 Bits 8-11
 For VRAM-B1 timing T1
 VCP2B10 to VCP2B13
 18001CH
 Bits 4-7
 For VRAM-B1 timing T2
 VCP3B10 to VCP3B13
 18001CH
 Bits 0-3
 For VRAM-B1 timing T3
 VCP4B10 to VCP4B13
 18001EH
 Bits 12-15
 For VRAM-B1 timing T4
 VCP5B10 to VCP5B13
 18001EH
 Bits 8-11
 For VRAM-B1 timing T5
 VCP6B10 to VCP6B13
 18001EH
 Bits 4-7
 For VRAM-B1 timing T6
 VCP7B10 to VCP7B13
 18001EH
 Bits 0-3
 For VRAM-B1 timing T7

If you do not split VRAM in two, the value of this register is ignored.

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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 3 RAM
Copyright SEGA ENTERPRISES, LTD., 1997