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"HARDWARE MANUAL" SCU User's Manual

1. Write protection to A-Bus by SCU-DMA

2. Read-protected by SCU-DMA from VDP2 area

3. Write access to the VDP1 register is done in words (2 bytes).

4. SCU-DMA cannot be used for WORKRAM-L (Notes)

5. Always use cache-through address to access SCU register

6. Write protection to unused area (address 25FE00ACH, etc.)

7. Write protection to interrupt status register (25FE00A4H)

8. A-Bus ← → B-Bus DMA access prohibited from CPU running A-Bus and B-Bus

9. Prohibition of setting A-Bus look-ahead valid bit

10. Address change of A-Bus interrupt acknowledge register (address 25FE00A8H)

11. Write limit of A-Bus setting register

12. Waiting for A-Bus ← → B-Bus SCU-DMA to start when CPU is written to A-Bus and B-Bus

13. Delete DMA status register (addresses 25FE0070H to 25FE007CH)

14. Deleted the function of the DMA forced stop register (address 25FE0060H)

15. Do not read the number of transferred bytes in the DMA transfer register (write only)

16. Restriction by access address of DMA read address addition value

17. Address addition value bit value when DMA read address update bit is set

18. Restriction by access address of DMA write address addition value

19. Address addition value bit value when the write address update bit of DMA is set

20. 2 channels can be used simultaneously for DMA

21. Specification change of DMA activation method

22. Specifications when there is a DMA activation trigger during DMA execution

23. Write protection to the corresponding level register while DMA is running

24. DMA illegal interrupt not occurred during DMA execution in indirect mode

25. DMA indirect mode table specification change

26. Clear program end interrupt flag when DSP starts

27. Limitation of address addition value when transferring DSP DMA instruction from B-Bus to DSP DATA RAM

28. DMA operation slows down when BREAK is used when debugging with ICE.

29. Be sure to enable BREQ when debugging with ICE.

30. Precautions when using the timer 0 compare register (address 25FE0090H)

31. Precautions when using the timer 1 set register (address 25FE0094H)

32. A-Bus, B-Bus area (2000000H ~ 5FFFFFFH) Precautions for read access

33. Initialization of A-Bus refresh during POWER ON RESET (address 25FE00B8H)

34. Initial value of SDRAM selection bit (address 25FE00C4 _H )

35. Do not start DMA level 2 while DMA level 1 is running

36. Precautions when reading the DSP program control port (address 25FE0080 _H )