STN-39

Supplementary information on the number of bytes transferred by SCU-DMA

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Contents

■ Operation when the number of DMA transfer bytes is set to '0'

When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers is the maximum value for each setting.

■ Supplementary information on the number of bytes transferred by SCU-DMA

When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers is the maximum for each setting.

<Table / Number of bytes transferred>

	Direct mode		Indirect mode
Transfer level	Register setting value	Number of bytes transferred	Transfer count setting value	Number of bytes transferred
LEVEL 0	00000H 00001H 00002H :: FFFFFH	100000H bytes 000001H bytes 000002H bytes :: 0FFFFFH bytes	00000H 00001H 00002H :: FFFFFH	100000H bytes 000001H bytes 000002H bytes :: 0FFFFFH bytes
LEVEL 1	000H 001H 002H :: FFFH	1000H bytes 0001H bytes 0002H bytes :: 0FFFH bytes	00000H 00001H 00002H :: FFFFFH	100000H bytes 000001H bytes 000002H bytes :: 0FFFFFH bytes
LEVEL 2	000H 001H 002H :: FFFH	1000H bytes 0001H bytes 0002H bytes :: 0FFFH bytes	00000H 00001H 00002H :: FFFFFH	100000H bytes 000001H bytes 000002H bytes :: 0FFFFFH bytes
DSP	00H 01H 02H :: FFH	100H word 001H word 002H word :: 0FFH word

• Note: The transfer unit of DMA for DSP is word unit (4 bytes).
• Indirect mode allows DMA transfers of up to 100,000 Hbytes at levels 0 to 2.
• For DSP DMA, setting '0' maximizes the number of transfers. However, in DMA for built-in RAM, one RAM has only 40H words, so if a larger number of transfer bytes is specified, the same address will be overwritten repeatedly.
  (The DSP DMA does not transfer access to another address, but the CPU read / write transfers access to another RAM.)

■ Transfer example

For DMA settings where transfer source = 6001000H address, transfer destination = 00H address of RAM0, and number of transfer bytes = 00H.

Address 6001000H → Address 00H of RAM0 (1st word data)
Address 6001004H → Address 01H of RAM0 (second word data)
Address 6001008H → Address 02H of RAM0 (3rd word data)
::
60010FCH address → 3FH address of RAM0 (64th word data)
Address 6001100H → Address 00H of RAM0 (65th word data) ← 1st word is overwritten
Address 6001104H → Address 01H of RAM0 (66th word data)
::
60013 FAH address → 3EH address of RAM0 (data of the 255th word)
60013 FCH address → 3FH address of RAM0 (256th word data) Maximum number of transfers

■ Reference

"HARDWARE MANUAL / SCU User's Manual"
CPU-DMA direct mode ● Number of bytes transferred