★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
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SCU User's Manual / Chapter 3 Register Details

■ 3.2 DMA control register

The DMA control register consists of the following registers.

◆ Level 2-0 DMA set register

There are three DMA levels, from level 2 with the highest priority to level 0 with the lowest priority.

● Read address
Figure 3.1 shows the details of the read address register. There are two modes of DMA, direct mode and indirect mode, and the meaning of the value changes in each mode.

Figure 3.1 Level 2-0 read address (registers: D0R, D1R, D2R) Initial value indefinite
bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE0000 (level 0)
25FE0020 (level 1)
25FE0040 (level 2)
 − − − − − 1 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four twenty five 26 27
 Read address (1 to 27 [bit 26 to 0] in Fig. 3.1 )
 DxR26-0 [x = 2-0] (R / W) DMA level 2-0 Read address bit26-0
 In direct mode, the stored value is the forwarding address. On the other hand, it has no meaning in indirect mode. While DMA is operating, registers at that level are write-protected. All address values are expressed in bytes.
 ● Export address
 Figure 3.2 shows the details of the write address register. There are two modes of DMA, direct mode and indirect mode, and the meaning of the value changes in each mode.
 Figure 3.2 Level 2-0 write address (registers: D0W, D1W, D2W) Initial value indefinite
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE0004 (level 0)
25FE0024 (level 1)
25FE0044 (level 2)
 − − − − − 1 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four twenty five 26 27
 Write address ( 1-27 [bit 26-0] in Figure 3.2 )
 DxW26-0 [x = 2-0] (R / W) DMA level 2-0 Write address bit26-0
 In direct mode, the stored value is the forwarding address. On the other hand, in the indirect mode, the address where the transfer source address of the first DMA transfer is stored is stored. While DMA is operating, registers at that level are write-protected. All address values are expressed in bytes.
 ● Number of bytes transferred
 Stores the number of bytes to be transferred by DMA. Figure 3.3 shows the details of the number of bytes transferred at level 0, and Figure 3.4 shows the details of the number of bytes transferred at level 2-1.
 Figure 3.3 Level 0 Number of bytes transferred (register: D0C) Initial value indefinite
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE0008 (level 0)
 − − − − − − − − − − − − 1 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15 16 17 18 19 20
 Level 0 Number of bytes transferred ( 1 to 20 [bit 19 to 0] in Fig. 3.3 )
 D0C19-0 (W) DMA level 0 Count bit19-0
 Stores the number of bytes of DMA transfer operating at level 0. While DMA is operating, registers at that level are write-protected. This register can be set up to 1MByte.
 Figure 3.4 Level 2-1 Number of bytes transferred (registers: D1C, D2C) Initial value indefinite
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE0028 (level 1)
25FE0048 (level 2)
 − − − − − − − − − − − − − − − − − − − − 1 2 3 4 5 6 7 8 9 Ten 11 12
 Level 2-1 Number of bytes transferred ( 1 to 12 [bit 11 to 0] in Fig. 3.4 )
 DxC11-0 [x = 2-1] (W) DMA level 2-1 Count bit 11-0
 Stores the number of bytes of DMA transfer operating at level 2 or 1. While DMA is operating, registers at that level are write-protected. This register can be set up to 4KByte.
 Do not read the number of transferred bytes in the DMA transfer register
 The value read from the number of bytes transferred in the DMA transfer register is not guaranteed. This register cannot be read. It becomes a light-only register.
 ■ Operation when the number of DMA transfer bytes is set to '0'
 When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers is the maximum value for each setting.
 detail:
 Developer's Information STN-39 / Supplementary information on the number of bytes transferred by SCU-DMA
 ● Addition value register
 Figure 3.5 shows the details of the adder register.
 Figure 3.5 Level 2-0 address addition value (registers: D0AD, D1AD, D2AD) Initial value 00000101H
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE000C (level 0)
25FE002C (Level 1)
25FE004C (level 2)
 − − − − − − − − − − − − − − − − − − − − − − − 1 − − − − − 2 3 4
 Read address addition value ( 1 [bit 8] in Fig. 3.5 )
 DxRA [x = 2-0] (W) DMA level 2-0 Read address Addition data bit
 Specifies the number of bytes to add to the read address. Table 3.2 shows the read address addition values. This is valid only in the CS2 space of A-Bus, otherwise set 1B. While DMA is operating, registers at that level are write-protected.
 Table 3.2 Read address addition value
 DxRA (x = 2-0)
 Contents
 0
 Do not add.
 1
 Add 4 bytes.
 Write address addition value ( 2 to 4 [bit 2 to 0] in Fig. 3.5 )
 DxWA3-0 [x = 2-0] (W) DMA level 2-0 Write address Addition data bit3-0
 Specifies the number of bytes to add to the write address. Table 3.3 shows the write-out address addition values. This is valid when writing to B-Bus, and only 000B or 010B of data can be set when writing to CS2 space of A-Bus. When writing to other than A-Bus or B-Bus, set the data to 010B. While DMA is operating, registers at that level are write-protected.
 Table 3.3 Export address addition value
 DxWA (x = 2-0)
 Contents
 000B
 Do not add
 001B
 Add 2 bytes
 010B
 Add 4 bytes
 011B
 Add 8 bytes
 100B
 Add 16 bytes
 101B
 Add 32 bytes
 110B
 Add 64 bytes
 111B
 Add 128 bytes
 There is a regulation as shown in Fig. 3.6 regarding this write address addition value. As shown in this figure, the SCU and B-Bus communicate in 32-bit units, but the B-Bus and processor communicate in 16-bit units. Therefore, as shown in Figure 3.7, when transferring data from A to D from the SCU to the processor, the SCU can transfer A to D to the processor at once to B-Bus, but B-Bus to the processor. On the other hand, there is no choice but to divide and transfer to A to B and C to D. From this, the write address addition value of B-Bus is in units of 2 bytes, so the difference between address 2 and address 1 can be specified as the write address addition value as shown in Fig. 3.8.
 Figure 3.6 Communication unit between SCU and processor
 Figure 3.7 Specific example of transfer between SCU and processor
 Figure 3.8 Specifying the write-out address addition value
 Address 1-Address 2 can be specified by "Write address addition value"
 <Restrictions on addition value register>
 Restriction by access address of DMA read address addition value
 The value that can be set for the read address addition value changes depending on the access address. This also applies to DSP DMA instructions.
 External area 4 area (A-Bus I / O area) → 0b and 1b can be set
 Other → Only 1b can be set
 Address addition value when DMA read address update bit is set Bit setting value
 When the read address update bit is "1b", the read address addition value bit must be "1b".
 Restriction by the access address of the write addition value of DMA
 The value that can be set for the write-out address addition value changes depending on the access address. This also applies to DSP DMA instructions.
 WORKRAM-H → 010b can be set
 External areas 1-3 areas → 010b can be set
 External area 4 area (A-Bus I / O area) → 000b,010b can be set
 VDP1, VDP2, SCSP → All settings are possible
 Address addition value when setting the write address update bit of DMA The set value of the bit
 When the write address update bit of DMA is "1b", the write address addition value bit must be set as follows depending on the bus space to be accessed.
 External area 1-4 area (A-Bus) → 010b can be set
 VDP1, VDP2, SCSP (B-Bus) → 001b can be set
 WORKRAM-H (C-Bus) → 010b can be set
 ◆ DMA permission register
 A register that allows DMA to be executed. While DMA is operating, registers at that level are write-protected. Figure 3.9 shows the format of this register.
 Figure 3.9 Level 2-0 DMA Allow Bits (Registers: D0EN, D1EN, D2EN) Initial Value 00000000H
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE0010 (level 0)
25FE0030 (level 1)
25FE0050 (level 2)
 − − − − − − − − − − − − − − − − − − − − − − − 1 − − − − − − − 2
 DMA permission bit ( 1 [bit 8] in Fig. 3.9 )
 DxEN [x = 2-0] (W) DMA level 2-0 ENable bit
 Bits that allow DMA to be executed. Set this flag to 1 to allow DMA. After this, DMA can be started, so set other necessary data in advance.
 DMA activation bit ( 2 [bit 0] in Fig. 3.9 )
 DxGO [x = 2-0] (W) DMA level 2-0 GO bit
 The bit that starts the execution of DMA. This bit is valid only when the start factor bit is 111B, and is set to 1 when starting DMA. One set fires DMA once.
 ◆ DMA mode, address update, start factor selection register
 Registers that specify the DMA mode (direct or indirect mode), address update (hold or update settings), and start factor selection. Figure 3.10 shows the details of this register. While DMA is operating, registers at that level are write-protected.
 Figure 3.10 Level 2-0 DMA mode, address update, start factor selection register (registers: D0MD, D1MD, D2MD) Initial value 00000007H
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
25FE0014 (level 0)
25FE0034 (level 1)
25FE0054 (level 2)
 − − − − − − − 1 − − − − − − − 2 − − − − − − − 3 − − − − − 4 5 6
 DMA mode bit ( 1 [bit 24] in Fig. 3.10 )
 DxMOD [x = 2-0] (W) DMA level 2-0 MODe bit
 Determines the DMA mode. A value of 0 indicates a direct mode, and a value of 1 indicates an indirect mode.
 Read address update bit ( 2 [bit 16] in Fig. 3.10 )
 DxRUP [x = 2-0] (W) DMA level 2-0 Read address renewal UP bit
 Determines whether to keep or update the value at the time of setting for the read address. A value of 0 means retention, and a value of 1 means update. For details on the operation, refer to the specific usage example in Section 2.1, "DMA Transfer".
 Write address update bit ( 3 [bit 8] in Fig. 3.10 )
 DxWUP [x = 2-0] (W) DMA level 2-0 Write address renewa UP bit
 Decides whether to keep or update the value at the time of setting for the write address. A value of 0 means retention, and a value of 1 means update. For details on the operation, refer to the specific usage example in Section 2.1, "DMA Transfer".
 DMA activation factor selection bit ( 4 to 6 [bit 2 to 0] in Fig. 3.10 )
 DxFT2-0 [x = 2-0] (W) DMA level 2-0 starting FacTor bit2-0
 DMA is activated by setting the DMA allow bit and receiving an external signal selected by the activation factor selection bit. However, when the activation factor bit is 111B, DMA is activated by setting the DMA activation bit.
 Table 3.4 Details of activation factors
 Start factor bit (x = 2-0)
 Trigger factor
 DxFT2
 DxFT1
 DxFT0
 0
 0
 0
 Allow set of bits and V-blank-IN signal reception
 0
 0
 1
 Allow set of bits and V-blank-OUT signal reception
 0
 1
 0
 Allow set of bits and H-blank-IN signal reception
 0
 1
 1
 Allow set of bits and timer 0 signal reception
 1
 0
 0
 Allow set of bits and timer 1 signal reception
 1
 0
 1
 Allow set of bits and sound-Req signal reception
 1
 1
 0
 Allow set of bits and receive sprite drawing end signal
 1
 1
 1
 Set of allow bits and set of DMA start bits
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