★ HARDWARE Manual ★ SCU User's Manual ★ 3.1 Register List
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SCU User's Manual / Chapter 3 Register Details

■ 3.4 Timer register

◆ Timer 0 compare register

Figure 3.18 shows the details of the timer 0 compare register. (Timer 0 is a counter that counts up when an H-blank-IN signal is received and is cleared when a V-blank-END signal is received.)

Figure 3.18 Timer 0 compare register (register: T0C) Initial value undefined
bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE0090 − − − − − − − − − − − − − − − − − − − − − − 1 2 3 4 5 6 7 8 9 Ten
 Timer 0 compare data ( 1 to 10 [bit 9 to 0] in Fig. 3.18 )
 T0C9-0 (W) Timer 0 Compare data bit9-0
 When the value of timer 0 becomes equal to the value of this register, a timer 0 interrupt is generated.
 <Precautions when using the timer 0 compare register>
 A 10-bit data set is possible, but if an impossible data is set, an interrupt will not occur. Be sure to set a value within the usable range.
 As an example, in the case of NTSC non-interlaced (263 lines per screen, 224 lines effective screen), an interrupt is generated as shown below.
 T0C9-0
 = 1
 Occurs at the beginning of HBLANK-IN just before the first line of the valid screen
 T0C9-0
 = 2
 Occurs at the beginning of HBLANK-IN just before the first two lines of the valid screen
 T0C9-0
 = 224
 Occurs at the beginning of HBLANK-IN just before the last line of the valid screen
 T0C9-0
 = 225
 Occurs at the beginning of HBLANK-IN immediately after the valid screen ends
 T0C9-0
 = 263
 Occurs at the beginning of HBLANK-IN immediately before the 1st line before the valid screen starts
 T0C9-0
 = 264 to 1023
 No interrupt occurs
 T0C9-0
 = 0
 An interrupt occurs at the same timing as VBLANK-OUT
 ◆ Timer 1 set data register
 Figure 3.19 shows the details of the timer 1 set data register. (Timer 1 sets the data in this register when receiving an H-blank-IN signal, automatically counts down at 7MHz, and issues an interrupt when the value of timer 1 becomes 0.)
 Figure 3.19 Timer 1 set data register (register: T1S) Initial value undefined
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE0094 − − − − − − − − − − − − − − − − − − − − − − − 1 2 3 4 5 6 7 8 9
 Timer 1 set data ( 1 to 9 [bit 8 to 0] in Fig. 3.19 )
 T1S8-0 (W) Timer 1 Set data bit8-0
 Set the value set in timer 1.
 <Precautions when using the timer 1 set data register>
 The value of the timer 1 set data register is loaded into timer 1 when "timer 1 is stopped and HBLANK-IN occurs".
 If data larger than the number of lines is set in the timer 1 set data register, the timer 1 interrupt will not occur every line.
 [Count range]
 For 320 dots per line 1-1 AAH
 For 1 line 352 dots 1-1C6H
 For 424 dots per line 1 ~ D3H
 For 426 dots per line 1 ~ D4H
 (Note that if you specify a count of 0, it will be 512.)
 ◆ Timer 1 mode register
 Figure 3.20 shows the details of the timer 1 mode register. This register determines how to set the timer 1 to occur.
 Figure 3.20 Timer 1 mode register (register: T1MD) Initial value 00000000H
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE0098 − − − − − − − − − − − − − − − − − − − − − − − 1 − − − − − − − 2
 Timer 1 mode bit ( 1 [bit 8] in Fig. 3.20 )
 T1MD (W) Timer 1 MoDe bit
 This bit is used to specify the occurrence of timer 1. Table 3.6 shows the details of the occurrence.
 Table 3.6 Timer 1 occurrence Selection details
 T1MD
 Birth selection content
 0
 An interrupt occurs on each line.
 1
 Occurs only on the line specified by timer 0.
 Timer enable bit ( 2 [bit 0] in Figure 3.20 )
 TENB (W) Timer ENaBle bit
 A bit that turns timer operation on and off. Table 3.7 shows the operation details.
 Table 3.7 Timer operation details
 TENB
 Taima movement
 0
 Timer operation OFF
 1
 Timer operation ON
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