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SCU User's Manual / Chapter 3 Register Details

■ 3.5 Interrupt control register

◆ Interrupt mask register

Figure 3.21 shows the details of the interrupt mask register. When the register value is 0, interrupts are not masked, and when 1 is 1, interrupts are masked.

Figure 3.21 Interrupt mask register (register: IMS) Initial value 0000BFFFH
bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE00A0 − − − − − − − − − − − − − − − − 1 − 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15
 A-Bus interrupt mask bit ( 1 [bit 15] in Fig. 3.21 )
 IMS15 (W) Interrupt MaSk bit bit15
 Specifies whether to mask A-Bus interrupts.
 caution
 Be sure to mask the A-Bus interrupt mask bit (set "1") except for the control of a special cartridge connector.
 supplement
 "Special cartridge equipment" refers to "XBAND modem" and "NetLink modem". Applications that use these devices should not mask A-Bus external interrupts.
 Sprite drawing end interrupt mask bit ( 2 [bit 13] in Fig. 3.21 )
 IMS13 (W) Interrupt MaSk bit bit13
 Specifies whether to mask the interrupt at the end of sprite drawing.
 DMA illegal interrupt mask bit ( 3 [bit 12] in Fig. 3.21 )
 IMS12 (W) Interrupt MaSk bit bit12
 Specifies whether to mask DMA illegal interrupts.
 Level 0-DMA end interrupt mask bit ( 4 [bit 11] in Figure 3.21 )
 IMS11 (W) Interrupt MaSk bit bit11
 Level 0-Specifies whether to mask the DMA end interrupt.
 Level 1-DMA end interrupt mask bit ( 5 [bit 10] in Figure 3.21 )
 IMS10 (W) Interrupt MaSk bit bit10
 Level 1-Specifies whether to mask the DMA end interrupt.
 Level 2-DMA end interrupt mask bit ( 6 [bit 9] in Figure 3.21 )
 IMS9 (W) Interrupt MaSk bit bit9
 Level 2-Specifies whether to mask the DMA end interrupt.
 PAD interrupt mask bit ( 7 [bit 8] in Fig. 3.21 )
 IMS8 (W) Interrupt MaSk bit bit8
 Specifies whether to mask interrupts from the PAD.
 System manager interrupt mask bit ( 8 [bit 7] in Figure 3.21 )
 IMS7 (W) Interrupt MaSk bit bit7
 Specifies whether to mask interrupts from the system manager.
 Sound request interrupt mask bit ( 9 [bit 6] in Fig. 3.21 )
 IMS6 (W) Interrupt MaSk bit bit6
 Specifies whether to mask sound request interrupts.
 SP end interrupt mask bit ( 10 [bit 5] in Fig. 3.21 )
 IMS5 (W) Interrupt MaSk bit bit5
 Specifies whether to mask the DSP termination interrupt.
 Timer-1 interrupt mask bit ( 11 [bit 4] in Figure 3.21 )
 IMS4 (W) Interrupt MaSk bit bit4
 Specifies whether to mask the timer-1 interrupt.
 Timer-0 interrupt mask bit ( 12 [bit 3] in Figure 3.21 )
 IMS3 (W) Interrupt MaSk bit bit3
 Specifies whether to mask timer-0 interrupts.
 H-Blank-IN interrupt mask bit ( 13 [bit 2] in Figure 3.21 )
 IMS2 (W) Interrupt MaSk bit bit2
 H-Blank-Specifies whether to mask IN interrupts.
 V-Blank-OUT interrupt mask bit ( 14 [bit 1] in Figure 3.21 )
 IMS1 (W) Interrupt MaSk bit bit1
 V-Blank-Specifies whether to mask OUT interrupts.
 V-blank-IN interrupt mask bit ( 15 [bit 0] in Figure 3.21 )
 IMS0 (W) Interrupt MaSk bit bit0
 V-Blank-Specifies whether to mask IN interrupts.
 ◆ Interrupt status register
 Figure 3.22 shows the details of the interrupt status register.
 Figure 3.22 Interrupt status register (register: IST) Initial value 00000000H
 bit
 31
 twenty four
 twenty three
 16
 15
 8
 7
 0
 25FE00A4 1 2 3 4 5 6 7 8 9 Ten 11 12 13 14 15 16 − − 17 18 19 20 twenty one twenty two twenty three twenty four twenty five 26 27 28 29 30
 When writing to the interrupt status register, the bit that should be set as an interrupt generation may not be set. Therefore, writing to this register is prohibited.
 Table 3.8 Interrupt Status Bit Contents (R)
 Status Contents
 0 No interrupt has occurred
 1 Interrupt is occurring
 External interrupt status bits (1 to 16 [bit31 to 16] in Figure 3.22 )
 IST31-16 (R) Interrupt STatus bit bit 31-16
 Indicates the status of 16 external interrupts from external interrupt 15 (1 in the figure) to external interrupt 0 (16 in the figure).
 Sprite drawing end interrupt status bit ( 17 [bit 13] in Fig. 3.22 )
 IST13 (R) Interrupt STatus bit bit13
 Indicates the status of the interrupt at the end of sprite drawing.
 DMA illegal interrupt status bit ( 18 [bit 12] in Figure 3.22 )
 IST12 (R) Interrupt STatus bit bit12
 DMA Indicates the status of an illegal interrupt.
 Level 0-DMA end interrupt status bit ( 19 [bit 11] in Figure 3.22 )
 IST11 (R) Interrupt STatus bit bit11
 Level 0-Represents the status of DMA termination interrupts.
 Level 1-DMA end interrupt status bit ( 20 [bit 10] in Figure 3.22 )
 IST10 (R) Interrupt STatus bit bit10
 Level 1-Represents the status of the interrupt at the end of DMA.
 Level 2-DMA end interrupt status bit ( 21 [bit 9] in Figure 3.22 )
 IST9 (R) Interrupt STatus bit bit9
 Level 2-Represents the status of the end of DMA interrupt.
 PAD interrupt status bit ( 22 [bit 8] in Figure 3.22 )
 IST8 (R) Interrupt STatus bit bit8
 Represents the status of interrupts from the PAD.
 System manager interrupt status bit ( 23 [bit 7] in Figure 3.22 )
 IST7 (R) Interrupt STatus bit bit7
 Represents the status of interrupts from the system manager.
 Sound request interrupt status bit ( 24 [bit 6] in Figure 3.22 )
 IST6 (R) Interrupt STatus bit bit6
 Represents the interrupt status of sound requests.
 DSP end interrupt status bit ( 25 [bit 5] in Figure 3.22 )
 IST5 (R) Interrupt STatus bit bit5
 Indicates the status of the DSP end interrupt.
 Timer-1 interrupt status bit ( 26 [bit 4] in Figure 3.22 )
 IST4 (R) Interrupt STatus bit bit4
 Represents the interrupt status of timer-1.
 Timer-0 interrupt status bit ( 27 [bit 3] in Figure 3.22 )
 IST3 (R) Interrupt STatus bit bit3
 Represents the interrupt status of timer-0.
 H-Blank-IN interrupt status bit ( 28 [bit 2] in Figure 3.22 )
 IST2 (R) Interrupt STatus bit bit2
 H-Blank-Represents the IN interrupt status. ..
 V-Blank-OUT interrupt status bit ( 29 [bit 1] in Figure 3.22 )
 IST1 (R) Interrupt STatus bit bit1
 V-Blank-Represents the OUT interrupt status.
 V-blank-IN interrupt status bit ( 30 [bit 0] in Figure 3.22 )
 IST0 (R) Interrupt STatus bit bit0
 V-Blank-Represents the IN interrupt status.
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