★ HARDWARE Manual ★ VDP2 User's Manual ★ Chapter 5 Normal scroll screen
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VDP2 User's Manual / Chapter 5 Normal Scroll Screen

■ 5.3 Line & vertical cell scroll function

In the normal scroll screen, NBG0 and NBG1 have a line scroll function and a vertical cell scroll function. The line scroll function specifies horizontal and vertical screen scroll values and horizontal coordinate increments on a line-by-line basis. The vertical cell scroll function specifies the vertical screen scroll value for each horizontal cell. Both functions can be used regardless of cell format or bitmap format.

● Line scroll function

The line scroll function is a function that allows you to specify horizontal and vertical screen scroll values and horizontal coordinate increments in line units, and is specified in the line scroll table stored in VRAM. The data value of the line scroll table is specified as a relative value. The value specified in the screen scroll value register is added to the screen scroll value stored in the line scroll table to obtain the display coordinates. The interval for reading table data can be selected from four types: 1 line, 2 lines, 4 lines, and 8 lines. Vertical coordinates are used for vertical coordinate calculation when an interval of 2 lines or more is selected. The value of the increment register is used.
Do not set the horizontal coordinate increment beyond the setting of the reduction enable register. The line scroll function is shown in Figure 5.3.

Figure 5.3 Line scroll function
Line scroll table (VRAM) Horizontal coordinate increment　
→→→→ Scroll screen ┏━━━━━━━━━━━━━━━━━━┓ ┏━┯━┯━┯━┯━┯━┯━　
┃ 1st line horizontal screen scroll value ┃ ┐ ┌── → ┃ │ │ │ │ │ │ │ 1st line ┠──────────────────┨ │ │ ┣━ ┿━┿━┿━┿━┿━┿━　
┃ 1st line vertical screen scroll value ┃ ├ ┘ ┌─ → ┃ │ │ │ │ │ │ │ 2nd line ┠──────────────────┨ │ │ ┣━ ┿━┿━┿━┿━┿━┿━　
┃ 1st line horizontal coordinate increment ┃ ┘ │ ┃ │ │ │ │ │ │ │ 3rd line ┣━━━━━━━━━━━━━━━━━━┫ │ ┣━┿━┿━┿ ━┿━┿━┿━　
┃ 2nd line horizontal screen scroll value ┃ ┐ │ ┃ │ │ │ │ │ │ │ 4th line ┠──────────────────┨ │ │ ┣━┿━┿ ━┿━┿━┿━┿━　
┃ 2nd line vertical screen scroll value ┃ ├─┘ ┃ │ │ │ │ │ │ │ 5th line ┠──────────────────┨│┣━┿━┿ ━┿━┿━┿━┿━　
┃ 2nd line horizontal coordinate increment ┃ ┘ ┃ │ │ │ │ │ │ │　
┣━━━━━━━━━━━━━━━━━━┫　

The line scroll table stores the horizontal screen scroll value, the vertical screen scroll value, and the horizontal coordinate increment in order from the smallest address. The line scroll data to be stored consists only of the required data according to the line scroll register settings.
The configuration of each horizontal screen scroll value, vertical screen scroll value, and horizontal coordinate increment on the line scroll table is the same as the data configuration set in each register. The bit configuration of the line scroll table data is shown in Figure 5.4, and the configuration of the line scroll table is shown in Figure 5.5.

Figure 5.4 Bit configuration of line scroll table data
● Horizontal and vertical screen scroll value registers　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+ 0H │-│-│-│-│-┃ Integer part (11 bits) │
└─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+ 2H │ Decimal part (8 bits) ┃-│-│-│-│-│-│-│-│
└─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
● Horizontal coordinate increment　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+ 0H │-│-│-│-│-│-│-│-│-│-│-│-│-│ Integer part │
└─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+ 2H │ Decimal part (8 bits) ┃-│-│-│-│-│-│-│-│
└─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
[Note] "-" is ignored　
Figure 5.5 Example line scroll table
● When horizontal and vertical screen scroll values and horizontal coordinate increments are specified for each line　
Line scroll table (VRAM)　
MSB LSB
┌─────────────────────────┐
Line scroll ─ → + 00H │ Horizontal screen scroll value of the first line (integer part) │
Table address ├─────────────────────────┤
+ 02H │ Horizontal screen scroll value of the first line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ Vertical screen scroll value of the first line (integer part) │
├─────────────────────────┤
+ 06H │ Vertical screen scroll value of the first line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Horizontal coordinate increment of the first line (integer part) │
├─────────────────────────┤
+ 0AH │ Horizontal coordinate increment of the first line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ 2nd line horizontal screen scroll value (integer part) │
├─────────────────────────┤
+ 0EH │ 2nd line horizontal screen scroll value (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 10H │ Vertical screen scroll value of the second line (integer part) │
├─────────────────────────┤
+ 12H │ Vertical screen scroll value of the second line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 14H │ Horizontal coordinate increment of the second line (integer part) │
├─────────────────────────┤
+ 16H │ Horizontal coordinate increment of the second line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥

● When the vertical screen scroll value and horizontal coordinate increment are specified every two lines　
Line scroll table (VRAM)　
MSB LSB
┌─────────────────────────┐
Line scroll ─ → + 00H │ Vertical screen scroll value of the first line (integer part) │
Table address ├─────────────────────────┤
+ 02H │ Vertical screen scroll value of the first line (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ 1st and 2nd line horizontal coordinate increment (integer part) │
├─────────────────────────┤
+ 06H │ 1st and 2nd line horizontal coordinate increment (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Vertical screen scroll value of the 3rd line (integer part) │
├─────────────────────────┤
+ 0AH │ 3rd line vertical screen scroll value (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ 3rd and 4th line horizontal coordinate increment (integer part) │
├─────────────────────────┤
+ 0EH │ 3rd and 4th line horizontal coordinate increment (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
　
[Note] The vertical display coordinates of lines other than the specified line are
The vertical screen scroll value for the specified line plus the vertical coordinate increment.　

● When the horizontal screen scroll value and horizontal coordinate increment are specified every 4 lines (no vertical line scroll)
　
Line scroll table (VRAM)　
MSB LSB
┌─────────────────────────┐
Line scroll ─ → + 00H │ Horizontal screen scroll value for lines 1 to 4 (integer part) │
Table address ├─────────────────────────┤
+ 02H │ Horizontal screen scroll value for lines 1 to 4 (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ Horizontal coordinate increment of lines 1 to 4 (integer part) │
├─────────────────────────┤
+ 06H │ Horizontal coordinate increment of lines 1 to 4 (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Horizontal screen scroll value of the 5th to 8th lines (integer part) │
├─────────────────────────┤
+ 0AH │ Horizontal screen scroll value of the 5th to 8th lines (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ Horizontal coordinate increment of 5th to 8th lines (integer part) │
├─────────────────────────┤
+ 0EH │ Horizontal coordinate increment of 5th to 8th lines (decimal part) │
┝━━━━━━━━━━━━━━━━━━━━━━━━━┥

● Vertical cell scroll function

The vertical cell scroll function is a function that allows you to specify the vertical screen scroll value for each area vertically divided by the horizontal cell unit, and specifies it in the vertical cell scroll table stored in VRAM. The data value of the vertical cell scroll table is specified as a relative value. The value specified in the screen scroll value register is added to the screen scroll value stored in the vertical cell scroll table to obtain the display coordinates. When displaying in bitmap format, you can specify it horizontally in units of 8 dots.
In the normal scroll screen, only NBG0 and NBG1 have the vertical cell scroll function. The vertical cell scroll function and the mosaic function cannot be used at the same time, and the mosaic function has priority.
The vertical cell scroll function is shown in Figure 5.6.

Figure 5.6 Vertical cell scroll function
Vertical cell scroll table (VRAM)　
┌─────────────────┐　
│ Vertical screen scroll value of the first cell │ ──┐　
├─────────────────┤ │　
│ Vertical screen scroll value of the second cell │ ──┼─┐　
├─────────────────┤ │ │ │　
│ Vertical screen scroll value of the 3rd cell │ ──┼─┼─┐　
├─────────────────┤ │ │ │ │　
│ │ │ │ │　
↓ ↓ ↓　
│ │ │ │ │ │ │ │ │ │ │　
─┼─┼─┼─┼─┼─┼─┼─┼─┼─　
│ ┏┿━┿━┿━┿━┿━┿━┿━┿━━ TV screen ─┼╂┼─┼─┼─┼─┼─┼─┼─┼─　
│ ┃ │ │ │ │ │ │ │ │ │ │　
─┼╂┼─┼─┼─┼─┼─┼─┼─┼─　
│ ┃ │ │ │ │ │ │ │ │ │ │　
─┼╂┼─┼─┼─┼─┼─┼─┼─┼─　
│ ┃ │ │ │ │ │ │ │ │ │ │　
─┼╂┼─┼─┼─┼─┼─┼─┼─┼─　
│ ┃ │ │ │ │ │ │ │ │ │ │　
─┼╂┼─┼─┼─┼─┼─┼─┼─┼─　
┃　
├─┤　
↑　
Vertical screen scroll value effective area of the first cell　
The bit configuration of the vertical screen scroll value is the same as when it is set in each register. In addition, the data in the vertical cell scroll table is set in order from the data for the cell on the left side of the TV screen.
When both NBG0 and NBG1 use the vertical cell scroll function, store each vertical cell scroll table data alternately for NBG0 and NBG1 for one cell at a time.

The bit configuration of the vertical cell scroll table data is shown in Figure 5.7, and the configuration of the vertical cell scroll table is shown in Figure 5.8.

Figure 5.7 Data structure on a vertical cell scroll table
● Vertical screen scroll value　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
+ 0H │-│-│-│-│-┃ Integer part (11 bits) │
└─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┘
　
Bit FE DC B A 9 8 7 6 5 4 3 2 1 0　
┌─┬─┬─┬─┬─┬─┬─┬─┰─┬─┬─┬─┬─┬─┬─┬─┐
+ 2H │ Decimal part (8 bits) ┃-│-│-│-│-│-│-│-│
└─┴─┴─┴─┴─┴─┴─┴─┸─┴─┴─┴─┴─┴─┴─┴─┘
　
[Note] "-" is ignored　
Figure 5.8 Example of vertical cell scroll table
● When scrolling vertical cells only for NBG0　
Vertical cell scroll table (VRAM)　
MSB LSB
┌──────────────────────────┐
Vertical cell scroll → + 00H │ Vertical screen scroll value / integer part of the first cell of NBG0 │
Table address ├──────────────────────────┤
+ 02H │ NBG0 1st cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ Vertical screen scroll value / integer part of the second cell of NBG0 │
├──────────────────────────┤
+ 06H │ NBG0 2nd cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Vertical screen scroll value / integer part of the 3rd cell of NBG0 │
├──────────────────────────┤
+ 0AH │ NBG0 3rd cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ NBG0 4th cell vertical screen scroll value / integer part │
├──────────────────────────┤
+ 0EH │ NBG0 4th cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 10H │ Vertical screen scroll value / integer part of the 5th cell of NBG0 │
├──────────────────────────┤
+ 12H │ Vertical screen scroll value / decimal part of the 5th cell of NBG0 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥

● When scrolling vertical cells only for NBG1　
Vertical cell scroll table (VRAM)　
MSB LSB
┌──────────────────────────┐
Vertical cell scroll → + 00H │ Vertical screen scroll value / integer part of the first cell of NBG1 │
Table address ├──────────────────────────┤
+ 02H │ Vertical screen scroll value / decimal part of the first cell of NBG1 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ Vertical screen scroll value / integer part of the second cell of NBG1 │
├──────────────────────────┤
+ 06H │ Vertical screen scroll value / decimal part of the second cell of NBG1 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Vertical screen scroll value / integer part of the 3rd cell of NBG1 │
├──────────────────────────┤
+ 0AH │ Vertical screen scroll value / decimal part of the 3rd cell of NBG1 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ NBG1 4th cell vertical screen scroll value / integer part │
├──────────────────────────┤
+ 0EH │ NBG1 4th cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 10H │ Vertical screen scroll value / integer part of the 5th cell of NBG1 │
├──────────────────────────┤
+ 12H │ Vertical screen scroll value / decimal part of the 5th cell of NBG1 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥

● When scrolling the vertical cells of NBG0 and NBG1　
Vertical cell scroll table (VRAM)　
MSB LSB
┌──────────────────────────┐
Vertical cell scroll → + 00H │ Vertical screen scroll value / integer part of the first cell of NBG0 │
Table address ├──────────────────────────┤
+ 02H │ NBG0 1st cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 04H │ Vertical screen scroll value / integer part of the first cell of NBG1 │
├──────────────────────────┤
+ 06H │ Vertical screen scroll value / decimal part of the first cell of NBG1 │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 08H │ Vertical screen scroll value / integer part of the second cell of NBG0 │
├──────────────────────────┤
+ 0AH │ NBG0 2nd cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 0CH │ NBG1 2nd cell vertical screen scroll value / integer part │
├──────────────────────────┤
+ 0EH │ NBG1 2nd cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥
+ 10H │ Vertical screen scroll value / integer part of the 3rd cell of NBG0 │
├──────────────────────────┤
+ 12H │ NBG0 3rd cell vertical screen scroll value / decimal part │
┝━━━━━━━━━━━━━━━━━━━━━━━━━━┥

● Line & vertical cell scroll control register

The line & vertical cell scroll control register controls the line scroll function and the vertical cell scroll function. A write-only 16-bit register located at address 18909AH. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

SCRCTL 18009AH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 ---
 ---
 N1LSS1
 N1LSS0
 N1LZMX
 N1LSCY
 N1LSCX
 N1VCSC

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 ---
 ---
 N0LSS1
 N0LSS0
 N0LZMX
 N0LSCY
 N0LSCX
 N0VCSC

　　
Line scroll interval bit : Line scroll select bit (N0LSS1, N0LSS0, N1LSS1, N1LSS0)
Specifies the interval at which line scroll table data is read from the table. The interval depends on the interlace settings on the TV screen.

N0LSS1, N0LSS0 18009AH Bits 5,4 For NBG0
N1LSS1, N1LSS0 18009AH Bits 13,12 For NBG1

NxLSS1 NxLSS0 Interlace settings
Non-interlaced Monodense interlacing Dense interlace
 0
 0
 For each line Every 2 lines For each line
 0
 1
 Every 2 lines Every 4 lines Every 2 lines
 1
 0
 Every 4 lines Every 8 lines Every 4 lines
 1
 1
 Every 8 lines Every 16 lines Every 8 lines
Note The x in the bit name can be 0 or 1.

When reading the data in the line scroll table at intervals of two or more lines, the line scroll data read before is used for the horizontal screen scroll value and the horizontal coordinate increment of the lines that are not read. In addition, the vertical screen scroll value is calculated from the previously read line scroll data and the value of the vertical coordinate increment register.

　　
Line zoom enable bit : Line zoom X enable bit (N1LZMX, N0LZMX)
Specifies whether to scale horizontally on a line-by-line basis.

N0LZMX 18009AH Bit 3 For NBG0
N1LZMX 18009AH Bit 11 For NBG1

NxLZMX process
 0
 Does not scale horizontally on a line-by-line basis
 1
 Scales horizontally in line units
Note The x in the bit name can be 0 or 1.

When using this feature, be sure to store the horizontal coordinate increments in the VRAM line scroll table. The horizontal coordinate increment should not exceed the reduction setting.

　　
Line scroll Y enable bit (for vertical screen scroll value) : Line scroll Y enable bit
(N1LSCY, N0LSCY)
Specifies whether to scroll vertically line by line.

N0LSCY 18009AH Bit 2 For NBG0
N1LSCY 18009AH Bit 10 For NBG1

NxLSCY process
 0
 Does not scroll vertically line by line
 1
 Scrolls vertically line by line
Note The x in the bit name can be 0 or 1.

When using this function, be sure to store the vertical screen scroll value in the VRAM line scroll table.

　　
Line scroll X enable bit (for horizontal screen scroll value) : Line scroll X enable bit
(N1LSCX, N0LSCX)
Specifies whether to scroll horizontally in line units.

N0LSCX 18009AH Bit 1 For NBG0
N1LSCX 18009AH Bit 9 For NBG1

NxLSCX process
 0
 Does not scroll horizontally line by line
 1
 Scrolls horizontally line by line
Note The x in the bit name can be 0 or 1.

When using this function, be sure to store the horizontal screen scroll value in the VRAM line scroll table.

　　

Vertical cell scroll enable bit : Vertical cell scroll enable bit
(N1VCSC, N0VCSC)
Specifies whether to perform vertical cell scrolling.

N0VCSC 18009AH Bit 0 For NBG0
N1VCSC 18009AH Bit 8 For NBG1

NxVCSC process
 0
 Does not perform vertical cell scrolling
 1
 Perform vertical cell scrolling
Note The x in the bit name can be 0 or 1.

When using the vertical cell scroll function, be sure to specify the access command for vertical cell scroll table data read in the VRAM cycle pattern register. Also, be sure to store the vertical cell scroll data in VRAM.
The vertical cell scroll function cannot be used at the same time as the mosaic function, and the mosaic function has priority.

Restrictions on vertical scrolling function
When changing from the state in which the vertical cell scroll function is used (ON) to the state in which it is not used (OFF), that is, when the vertical cell scroll enable bit (N0VCSC, N1VCSC) is changed from "1" to "0", the VRAM cycle pattern register The access command (Ch or Dh) for the vertical cell scroll table data read for NBG0 or NBG1 set to is also required to be changed to the access command (Fh) that says " Do not access" during the same V blank period.

This restriction must also be observed when changing from using the vertical cell scroll function of NBG0 and NBG1 at the same time to not using either of the vertical cell scroll functions.

Examples of restrictions

Example 1: When using the vertical cell scroll function of NBG0

When the settings when using the vertical cell scroll function are as follows:

<Settings>

To disable the vertical cell scroll function of NBG0 from this state, change to the following settings during the same V blank period.

<Settings>

Example 2: When using the vertical cell scroll function of NBG0 and NBG1 at the same time

When the settings when using the vertical cell scroll function are as follows:

<Settings>

To not use only the vertical cell scroll function of NBG1 from this state, change to the following settings during the same V blank period.

<Settings>

● Line scroll table address register

The line scroll table address register specifies the start address of the line scroll table. This is a write-only 32-bit register located at addresses 1800A0H to 1800A6H. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

LSTA0U 1800A0H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 ---
 ---
 ---
 ---
 ---
 ---
 ---
 ---

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 ---
 ---
 ---
 ---
 ---
 N0LSTA18
 N0LSTA17
 N0LSTA16

LSTA0L 1800A2H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 N0LSTA15
 N0LSTA14
 N0LSTA13
 N0LSTA12
 N0LSTA11
 N0LSTA10
 N0LSTA9
 N0LSTA8

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 N0LSTA7
 N0LSTA6
 N0LSTA5
 N0LSTA4
 N0LSTA3
 N0LSTA2
 N0LSTA1
 ---

LSTA1U 1800A4H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 ---
 ---
 ---
 ---
 ---
 ---
 ---
 ---

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 ---
 ---
 ---
 ---
 ---
 N1LSTA18
 N1LSTA17
 N1LSTA16

LSTA1L 1800A6H
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 N1LSTA15
 N1LSTA14
 N1LSTA13
 N1LSTA12
 N1LSTA11
 N1LSTA10
 N1LSTA9
 N1LSTA8

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 N1LSTA7
 N1LSTA6
 N1LSTA5
 N1LSTA4
 N1LSTA3
 N1LSTA2
 N1LSTA1
 ---

　　
Line scroll table address bit : Line scroll table address bit
(N0LSTA18 ~ N0LSTA16, N0LSTA15 ~ N0LSTA1, N1LSTA18 ~ N1LSTA16, N1LSTA15 ~ N1LSTA1)
Specifies the start address of the line scroll table in VRAM.

N0LSTA18 ~ N0LSTA16 1800A0H Bits 2-0 For NBG0 (upper bit)
N0LSTA15 ~ N0LSTA1 1800A2H Bits 15 to 1 For NBG0 (lower bit)
N1LSTA18 ~ N1LSTA16 1800A4H Bits 2-0 For NBG1 (upper bit)
N1LSTA15 ~ N1LSTA1 1800A6H Bits 15 to 1 For NBG1 (lower bit)

The actual start VRAM address is calculated by the following formula. If the VRAM capacity is 4M bits, the most significant bit of the address is ignored.

 (Line scroll table start address) = (Line scroll table address register value 18 bits) x 4H

● Vertical cell scroll table address register

The vertical cell scroll table address register specifies the start address of the vertical cell scroll table. This is a write-only 32-bit register located at addresses 18909CH to 18909EH. After turning on the power or resetting, the value will be cleared to 0, so be sure to set it.

VCSTAU 18009CH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 ---
 ---
 ---
 ---
 ---
 ---
 ---
 ---

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 ---
 ---
 ---
 ---
 ---
 VCSTA18
 VCSTA17
 VCSTA16

VCSTAL 18009EH
 15
 14
 13
 12
 11
 Ten
 09 09
 08 08
 VCSTA15
 VCSTA14
 VCSTA13
 VCSTA12
 VCSTA11
 VCSTA10
 VCSTA9
 VCSTA8

 07 07
 06 06
 05 05
 04
 03 03
 02 02
 01 01
 00
 VCSTA7
 VCSTA6
 VCSTA5
 VCSTA4
 VCSTA3
 VCSTA2
 VCSTA1
 ---

　
Vertical cell scroll table address bits: Vertical cell scroll table address bit ( VCSTA18~VCSTA1)
Specifies the start address of the vertical cell scroll table in VRAM.

VCSTA18 ~ VCSTA16 18009CH Bits 2-0
VCSTA15 ~ VCSTA1 18009EH Bits 15 to 1

The actual start VRAM address is calculated by the following formula. If the VRAM capacity is 4M bits, the most significant bit of the address is ignored.


(Vertical cell scroll table start address)
= (Vertical cell scroll table address register value 18 bits) x 4H

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★ HARDWARE Manual VDP2 User's Manual ★ Chapter 5 Normal scroll screen
Copyright SEGA ENTERPRISES, LTD., 1997