TVMD F 87654 210
180000H ■ □□□□□□ ■■■■■ □ ■■■
         │ │ │ │ │ │ └┴┴── HRESO 2,1,0 horizontal resolution │ │ │ │ └┴────── VRESO1,0 vertical resolution │ │ └┴──────── LSMD1 , 0 Interlaced mode │ └────────── BDCLMD border color mode └───────────────── DISP TV screen display

detail:

■ 2.4 TV screen mode register

reference:

■ 1.3 Scroll function

■ 2.1 TV screen mode

■ 2.2 Interlaced mode

■ 2.3 TV screen configuration

EXTEN F 98 10
180002H □□□□□□ ■■ □□□□□□ ■■
         │ │ │ └── EXBGEN external screen enabled　
         │ │ └─── DASEL image display area select │ └────────── EXSYEN external synchronization enabled　
         └─────────── EXLTEN External Latch Enable　

detail:

● External signal enable register

reference:

■ 2.3 TV screen configuration

■ 2.5 External signal and scanning status

TVSTAT F 98 3210
180004H □□□□□□ ■■ □□□□ ■■■■
           │ │ │ │ │ └── PAL TV system flag │ │ │ │ └─── ODD scanning field flag │ │ │ └──── HBLANK H blank flag │ │ └───── VBLANK V blank flag │ └ ────────── EXSYFG External Sync Flag └─────────── EXLTFG External Latch Flag　

detail:

● Screen status register

reference:

■ 2.3 TV screen configuration

■ 2.5 External signal and scanning status

VRSIZE F 3210
180006H ■ □□□□□□□□□□□ ■■■■
         │ └┴┴┴── VER3..0 version number └───────────────── VRAMSZ VRAM size

detail:

● VRAM size register

reference:

■ 1.2 Address map

■ 3.1 Address map

HCNT F 9876543210
180008H □□□□□□ ■■■■■■■■■■
         └┴┴┴┴┴┴┴┴┴── HCT9..0 H counter value

detail:

● H counter register

connection:

● V counter register

reference:

■ 2.5 External signal and scanning status

VCNT F 9876543210
18000AH □□□□□□ ■■■■■■■■■■
         └┴┴┴┴┴┴┴┴┴── VCT9..0 V counter value

detail:

● V counter register

connection:

● H counter register

reference:

■ 2.5 External signal and scanning status

         F 0
18000CH □□□□□□□□□□□□□□□□

	Access prohibited by users! !! !!

RAMCTL F DC 9876543210
18000EH ■ □ ■■ □□ ■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴── RDBSA0 rotation data bank specification (for VRAM-A0 or VRAM-A)
         │ │ │ │ │ │ │ │ │ └ ┴──── RDBSA1 rotation databank specification (for VRAM-A1)
         │ │ │ │ │ │ │ └ ┴────── RDBSB0 rotation databank specification (for VRAM-B0 or VRAM-B)
         │ │ │ │ │ └┴──────── RDBSB1 rotation databank specification (for VRAM-B1)
         ￨￨ ￨└────────── ￨ VRAMD VRAM mode (for the VRAM-A)
         │ │ │ └─────────── VRBMD VRAM mode (for VRAM-A)
         │ └┴────────────── CRMD color RAM mode └────────────────── CRKTE color RAM coefficient table enabled

detail:

● RAM control register

reference:

■ 1.2 Address map

■ 3.2 VRAM bank division

■ 3.4 Color RAM mode

■ 6.2 Rotation scroll screen display control

■ 6.4 Coefficient table control

CYCA0L F 0
180010H ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴ ┴ ┴ ── VCP3A03..0 VRAM-A3 (or VRAM-A) timing for T3 ─── VCP2A03..0 VRAM-A2 (or VRAM-A) timing for T2 │ │ │ │ └┴┴┴────────── VCP1A03..0 VRAM-A1 (or VRAM-A) ) For timing T1 └┴┴┴────────────── VCP0A03..0 For VRAM-A0 (or VRAM-A) timing T0

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCA0U F 0
180012H ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴ ┴ ┴ ── VCP7A03..0 VRAM-A3 (or VRAM-A) timing for T7 ─── VCP6A03..0 VRAM-A2 (or VRAM-A) timing for T6 │ │ │ │ └┴┴┴────────── VCP5A03..0 VRAM-A1 (or VRAM-A) ) For timing T5 └┴┴┴────────────── VCP4A03..0 For VRAM-A0 (or VRAM-A) timing T4

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCA1L F 0
180014H ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ | 0 VRAM-A1 timing for T2 │ │ │ │ └┴┴┴────────── VCP1A13..0 VRAM-A1 timing for T1 └┴┴┴───────── ───── VCP0A13..0 For VRAM-A1 timing T0

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCA1U F 0
180016H ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴ ┴ ┴ ── VCP7A13..0 VRAM-A1 timing for T7 │ │ │ │ │ │ │ 0 VRAM-A1 timing for T6 │ │ │ │ └┴┴┴────────── VCP5A13..0 VRAM-A1 timing for T5 └┴┴┴───────── ───── VCP4A13..0 VRAM-A1 for timing T4

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCB0L F 0
180018H ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴ ┴ ┴ ── VCP3B03..0 VRAM-B3 (or VRAM-B) timing for T3 ─── VCP2B03..0 VRAM-B2 (or VRAM-B) timing for T2 │ │ │ │ └┴┴┴────────── VCP1B03..0 VRAM-B1 (or VRAM-B) ) For timing T1 └┴┴┴────────────── VCP0B03..0 For VRAM-B0 (or VRAM-B) timing T0

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCB0U F 0
18001AH ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ │ └ ┴ ┴ ┴ ── VCP7B03..0 VRAM-B3 (or VRAM-B) timing for T7 ─── VCP6B03..0 VRAM-B2 (or VRAM-B) timing for T6 │ │ │ │ └┴┴┴────────── VCP5B03..0 VRAM-B1 (or VRAM-B) ) For timing T5 └┴┴┴────────────── VCP4B03..0 For VRAM-B0 (or VRAM-B) timing T4

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCB1L F 0
18001CH ■■■■■■■■■■■■■■■■
         │ │ │ │ │ │ │ │ │ | 0 VRAM-B1 timing for T2 │ │ │ │ └┴┴┴────────── VCP1B13..0 VRAM-B1 timing for T1 └┴┴┴───────── ───── VCP0B13..0 For VRAM-B1 timing T0

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period

CYCB1U F 0
18001EH ■■■■■■■■■■■■■■■■
         ￨￨￨￨￨￨￨￨￨￨￨￨└┴┴┴── VCP7B13..0 timing T7 of-B1 ￨￨￨￨￨￨￨￨└┴┴┴────── VRAM VCP6B13 .. 0 VRAM-B1 timing for T6 │ │ │ │ └┴┴┴────────── VCP5B13..0 VRAM-B1 timing for T5 └┴┴┴───────── ───── VCP4B13..0 VRAM-B1 timing for T4

detail:

● VRAM cycle pattern register

reference:

■ 3.3 VRAM access method during the display period