Chart table of contents

table

Chapter 2 Operation explanation

Table 2.1 Interrupt factors

Table 2.2 Generic term for interrupt factors

Chapter 3 Register Details

Table 3.1 Register list

Table 3.2 Read address addition value

Table 3.3 Export address addition value

Table 3.4 Details of activation factors

Table 3.5 RAM page selection

Table 3.6 Timer 1 occurrence Selection details

Table 3.7 Timer operation details

Table 3.8 Interrupt Status Bit Contents (R)

Table 3.9 A-Bus Interrupt Accessory Contents

Table 3.10 CS0 Spatial Burst Cycle Settings

Table 3.11 CS0 spatial normal cycle setting values

Table 3.12 CS0 Spatial Burst Length Settings

Table 3.13 CS0 spatial bus size settings

Table 3.14 CS1 Spatial Burst Cycle Settings

Table 3.15 CS1 spatial normal cycle setting values

Table 3.16 CS1 Spatial Burst Length Settings

Table 3.17 CS1 spatial bus size settings

Table 3.18 CS2 Spatial Burst Length Settings

Table 3.19 CS2 spatial bus size settings

Table 3.20 Spare space burst cycle settings

Table 3.21 Spare space normal cycle setting values

Table 3.22 Spare space burst length settings

Table 3.23 Spare space bus size settings

Table 3.24 Number of A-Bus refresh weights

Chapter 4 DSP control

Table 4.1 Features of data transfer from D0 bus to DSP

Table 4.2 Features of data transfer from DSP to D0 bus

figure

Chapter 2 Operation explanation

Figure 2.1 Basic operation of DMA transfer

Figure 2.2 DMA transferable area when booted from the main CPU

Figure 2.3 DMA transferable area when booted from DSP

Figure 2.4 Details of direct mode DMA transfer operation

Figure 2.5 Indirect mode DMA transfer flow

Figure 2.6 Details of indirect mode DMA transfer operation

Figure 2.7 Differences in DMA operation depending on the address update bit

Figure 2.8 Example of writing data

Figure 2.9 Contents of work RAM area

Figure 2.10 Example of DMA transfer execution by setting the address addition value

Figure 2.11 Blanking interrupt details

Figure 2.12 Timer 0 interrupt generation process

Figure 2.13 Timer 1 interrupt generation process (synchronized with timer 0)

Figure 2.14 Timer 1 interrupt generation process (asynchronous with timer 0)

Figure 2.15 Loading the DSP program Step1

Figure 2.16 Loading the DSP program Step2

Figure 2.17 Loading the DSP program Step3

Figure 2.18 DSP data access step1

Figure 2.19 DSP data access step2

Figure 2.20 DSP data access step3

Figure 2.21 Control to start execution of DSP program from CPU

Figure 2.22 Forced stop control of DSP program from CPU

Chapter 3 Register Details

Figure 3.1 Level 2-0 read address

Figure 3.2 Level 2-0 write address

Figure 3.3 Level 0 Number of bytes transferred

Figure 3.4 Level 2-1 Number of bytes transferred

Figure 3.5 Level 2-0 address addition value

Figure 3.6 Communication unit between SCU and processor

Figure 3.7 Specific example of transfer between SCU and processor

Figure 3.8 Specifying the write-out address addition value

Figure 3.9 Level 2-0 DMA Allow Bits

Figure 3.10 Level 2-0 DMA mode, address update, activation factor selection register

Figure 3.14 DSP program control port

Figure 3.15 DSP program RAM data port

Figure 3.16 DSP data RAM address port

Figure 3.17 DSP data RAM data port

Figure 3.18 Timer 0 compare register

Figure 3.19 Timer 1 set data register

Figure 3.20 Timer 1 mode register

Figure 3.21 Interrupt mask register

Figure 3.22 Interrupt status register

Figure 3.23 A-Bus Interrupt Acknowledgment Register

Figure 3.24 A-Bus setting register [CS0,1 space]

Figure 3.25 A-Bus setting register [CS2, spare space]

Figure 3.27 Timing when precharge insertion bit is set after writing

Figure 3.28 Timing when precharge insertion bit is set after reading

Figure 3.29 Difference in timing due to external weight valid bit setting

Figure 3.30 A-Bus refresh register

Figure 3.31 SCU SDRAM selection bits

Figure 3.32 SCU version register

Chapter 4 DSP control

Figure 4.1 DSP internal block diagram

Figure 4.2 Execution of JUMP instruction

Figure 4.3 Executing the LOOP program

Figure 4.5 Arithmetic instruction format

Figure 4.6 Load Immediate instruction format 1 (unconditional transfer)

Figure 4.7 Load Immediate instruction format 2 (conditional transfer)

Figure 4.8 DMA instruction format 1

Figure 4.9 DMA instruction format 2

Figure 4.10 JUMP instruction format

Figure 4.11 LOOP BOTTOM instruction format

Figure 4.12 END instruction format