SCSP User's Manual / Table of Contents

★ HARDWARE Manual ★ SCSP User's Manual

SCSP User's Manual

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Alphabet index

[Number] [A] [C] [D] [E] [F] [I] [K] [L] [M] [O] [P] [R] [S] [T]

▲ [Number]

Correspondence between 3-bit code and register

4SLOT configuration algorithm

7SLOT FM configuration

D / A converter output level

Sending level to D / A converter

Localization data by DIPAN

DMA controller block diagram

DMA transfer register

DMA transfer direction

DMA transfer interface

DSP configuration

DSP configuration diagram

DSP output stage adjustment unit

DSP control register

Buffer map in DSP

DSP input stage arithmetic adjustment unit

Localization calculation by DSP

DSP microprogram

DSP microprogram map

Localization data by EFPAN

FM configuration algorithm pattern

FM sound source configuration diagram

FM sound source method

Address pointer output value when FM speech synthesis is executed

Address displacement during FM synthesis

FM modulation control register

FNS.OCT parameter table

Relationship between the number of sources that can be input to IMXL and MIXS

KEY_ON and KEY_OFF sequences

AM modulation waveform by LFO

PM modulation waveform by LFO

LFO block diagram

LSI specifications

Relationship between MDXSL / MDYSL and slots

MDXSL / MDYSL calculation formula

MIDI-I / F block diagram

MIDI OUT section and interrupt generator section

Relationship between OCT and FNS

PCM sound source

RBL and ring buffer length

SCSP LSI specifications

SCSP common control register (figure)

SCSP common control register (list)

SCSP chip block diagram

SCSP and DAC connection

Operation of DSP in SCSP

SCSP memory map

Functions of SSCTL

Count cycle for TACTL, TBCTL, TCCTL settings

TL, attenuation and waveform amplitude

Wave data when bit4 = 1 of TL

Hiragana index

[Oh] [or] [is] [was] [Do not] [is] [or] [et al.] []

▲ [A]: Access overview; Attack state; Transition from attack state to decay 1; KEY-OFF during attack state transition; Address pointer; Address pointer output enlarged view; Phase adder; Interface (SCSP); Interface (sound CPU); Interface (main CPU); Interpolator; Effect data; Envelope generator; Sound data stack; Alternative loop; Sound source register; Sound source register allocation; Volume register
▲ [ka]: External input; EFSDL, EFPAN register address corresponding to each EFSDL, EXTS; Career; Clipping process; Wave data during clipping processing; Change in attenuation
▲ [Sa]: Final stage output adjustment unit; Definition of top slot; Shortest interrupt time and longest interrupt time; Sound CPU address 100400H, 100401H; Sound CPU interface; Sound CPU specifications; Interrupt vector table table for sound CPU; Sound system configuration; Sound system boot; Sound stack; Types of sound data; Sound memory configuration register; Sound memory map; Sound interrupt signal connection diagram @; The number of samples; System configuration; Frequency address pointer output value; Output mixer; Degree of amplitude modulation and frequency modulation; Time lag until a slot is written to the sound stack; Slot status register; Slot connection formula; Number of slot connections; Block diagram of slots; Slot averaging operation; Control register for each slot; Self feedback; Self-feedback modulation; St.; Real frequency for cents
▲ [ta]: Timer A increment cycle; Timer B increment cycle; Timer C increment cycle; Timer register; Direct audio adjustment unit; Path of direct component and effect component; Direct data; Multi-stage feedback; Decay 1 state; Decay 2 state; KEY-OFF during decay state transition; Digital mixer block diagram; Digital mixer block diagram
▲ [na]: Relationship between block diagram and LFO related to noise generation; Normal loop
▲ [ha]: Waveform RAM; Waveform address generation calculation unit; Waveform address generation / waveform data reading; Waveform address pointer; Waveform data buffer; Maximum displacement due to waveform read address; Oscillator frequency; Bread pot; Phase generator; Combined feedback; Composite modulation; Prescaler; Average calculation unit; Average calculation formula
▲ [Ma]: Mix register input level; Main CPU interface; Regarding communication between the main block and the sound block; Memory access priority; Memory address mapping diagram; Memory controller; Memory capacity; Modulation level; Modulator
▲ [Ra]: Reset vector; linear; Reverse loop; Release status; Loop control register; Loop type; Loop waveform; Maximum address displacement due to register setting value; Modulation degree by register setting value; Register map; Level calculation unit; Level multiplication part
▲ [Wa]: Interrupt signal; Interrupt control register; Interrupt relationship; Interrupt register bit support; Interrupt register bit factor; Interrupt level setting register format

★ HARDWARE Manual ★ SCSP User's Manual

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