Chart table of contents

table

Chapter 1 Sound system configuration

Table 1.1 Sound memory mapping (overview)

Table 1.2 Initialization setting data after reset

Table 1.3 Reset Vector

Table 1.4 Interrupt vector table for sound CPU Table

Table 1.5 Register setting table

Chapter 4 SCSP Register

Table 4.1 Address map by slot

Table 4.2 Control registers by slot

Table 4.3 SCSP common control registers

Table 4.4 Sound data stack

Table 4.5 DSP control register

Table 4.6 DSP microprogram

Table 4.7 Buffer map in DSP

Table 4.16 Relationship between MDXSL / MDYSL and slots

Table 4.10 Maximum address displacement due to register settings

Table 4.18 TL, attenuation and waveform amplitude

Table 4.12 Real frequencies for cents

Table 4.13 FNS.OCT parameter table

Table 4.14 Oscillator frequency

Table 4.15 AM modulation waveform by LFO

Table 4.16 PM modulation waveform by LFO

Table 4.17 Degree of Amplitude Modulation and Frequency Modulation

Table 4.18 Relationship between the number of sources that can be input to IMXL and MIXS

Table 4.19 Mix stack register input levels

Table 4.20 D / A converter output level

Table 4.21 Localization data by DIPAN

Table 4.22 Sending level to D / A converter

Table 4.23 Localization data by EFPAN

Table 4.24 EFSDL, EFPAN register addresses corresponding to each EFREG, EXTS

Table 4.25 Memory capacity

Table 4.26 Timer A increment cycle

Table 4.27 Timer B increment cycle

Table 4.28 Timer C increment cycle

Table 4.29 Count period for TACTL, TBCTL, TCCTL settings

Table 4.30 Shortest interrupt time and longest interrupt time

Table 4.31 Interrupt register bit factors

Table 4.32 DMA transfer direction

Table 4.33 DMA transfer

Table 4.34 RBL and ring buffer length

figure

Chapter 1 Sound system configuration

Figure 1.1 Sound block

Chapter 2 Overview of SCSP

Figure 2.3 Reset sequence (operation sequence diagram)

Figure 2.4 Interrupt relationship

Figure 3.1 CD-DA route

Figure 2.1 SCSP chip block diagram

Chapter 3 SCSP Function

Figure 3.1 Access overview

Figure 3.2 Memory access priority

Chapter 4 SCSP Register

Figure 4.1 SCSP Memory Map (1906 Word)

Figure 4.2 KEY_ON and KEY_OFF functions

Figure 4.3 Relationship between block diagram and LFO related to noise generation

Figure 4.4 Loop types

Figure 4.5 Loop waveform

Figure 4.6 KEY_OFF during attack state transition

Figure 4.7 KEY-OFF during decay state transition

Figure 4.8 Change in attenuation

Figure 4.9 Transition from attack state to decay 1 (1)

Figure 4.10 Transition from attack state to decay 1 (2)

Figure 4.11 Transition from attack state to decay 1 (3)

Figure 4.12 Slot block diagram

Figure 4.13 Waveform address generation calculation unit

Figure 4.14 Waveform address generation / waveform data reading

Figure 4.15 Enlarged view of address pointer output

Figure 4.16 Frequency address pointer output value

Figure 4.17 Address pointer output value when FM speech synthesis is executed (1)

Figure 4.18 Address pointer output value when FM speech synthesis is executed (2)

Figure 4.19 Normal loop

Figure 4.20 Reverse loop

Figure 4.21 Alternative loop

Figure 4.22 FM sound source configuration diagram

Figure 4.23 Average calculation formula

Figure 4.24 Slot arithmetic and sound stack status

Figure 4.25 Time difference between slots being written to the sound stack

Figure 4.26 Slot averaging operation

Figure 4.27 4-slot configuration algorithm

Figure 4.28 Slot 0 algorithm

Figure 4.29 Slot 2 algorithm

Figure 4.30 Slot 2 algorithm (by input slot)

Figure 4.31 Slot 3 algorithm

Figure 4.32 MDL modulation

Figure 4.33 Maximum displacement due to waveform read address

Figure 4.34 Address displacement during FM synthesis

Figure 4.35 Wave data during clipping processing

Figure 4.36 Number of slot connections

Figure 4.37 Self-feedback modulation

Figure 4.38 Multi-stage feedback

Figure 4.39 Combined feedback

Figure 4.40 Composite modulation

Figure 4.41 FM configuration algorithm pattern 1

Figure 4.42 FM configuration algorithm pattern 2

Figure 4.43 7-slot FM configuration

Figure 4.44 Wave data at TL bit4 = 1

Figure 4.45 Relationship between OCT and FNS

Figure 4.46 LFO block diagram

Figure 4.47 Digital mixer block diagram

Figure 4.48 Path of direct and effect components

Figure 4.49 Localization operation by DSP

Figure 4.50 Digital mixer block diagram

Figure 4.51 SCSP and DAC connections

Figure 4.52 Memory address mapping diagram

Figure 4.53 MIDI-I / F block diagram

Figure 4.54 MIDI OUT section and interrupt generator section

Figure 4.55 Sound interrupt signal connection diagram

Figure 4.56 Interrupt register bit support

Figure 4.57 Correspondence between 3-bit code and register

Figure 4.58 Interrupt level setting register format

Figure 4.59 DMA controller block diagram

Chapter 5 DSP Operations in SCSP

Figure 5.1 DSP configuration diagram