★ HARDWARE Manual ★ SCU User's Manual
SCU User's Manual Search
[A] [B] [C] [D] [E] [J] [L] [P] [R] [S] [V]
- ▲ [A]
- A-Bus
- A-Bus control register
- A-Bus setting register (CS0,1 space)
- A-Bus setting register (CS2, and spare space)
- A-Bus configuration register map
- Number of A-Bus refresh weights
- A-Bus refresh register
- A-Bus refresh register map
- A-Bus interrupt acknowledge content
- A-Bus interrupt acknowledge register
- A-Bus interrupt acknowledge register map
- ▲ [B]
- B-Bus
- ▲ [C]
- Forced stop control of DSP program from CPU
- Execution start control of DSP program from CPU
- CS0,1,2, A-Bus setting register in spare space
- CS0 spatial normal cycle setting value
- CS0 spatial bus size setting
- CS0 spatial burst cycle setting
- CS0 spatial burst length setting
- CS1 spatial normal cycle setting value
- CS1 space bus size setting value
- CS1 spatial burst cycle setting
- CS1 spatial burst length setting
- CS2 space bus size setting value
- CS2 spatial burst length setting
- ▲ [D]
- Features of data transfer from D0 bus to DSP
- DMA-illegal interrupt
- DMA permit register
- DMA end interrupt
- DMA control register
- DMA transfer basic operation
- Execution of DMA instruction
- DMA instruction format 1
- DMA instruction format 2
- DMA mode
- DMA mode, address update, start factor selection register
- Features of data transfer from DSP to D0 bus
- DMA transferable area when booted from DSP
- DSP end interrupt
- DSP control port
- DSP data RAM address port
- DSP data RAM address portmap
- DSP data RAM data port
- DSP data RAM data port map
- DSP data access Step1
- DSP data access Step2
- DSP data access Step3
- DSP internal block diagram
- DSP program RAM data port
- DSP program RAM data port map
- DSP program control port
- DSP program control portmap
- Loading the DSP program Step1
- Loading the DSP program Step2
- Loading the DSP program Step3
- ▲ [E]
- Execution of END instruction
- END instruction format
- ▲ [J]
- JUMP instruction format
- Execution of JUMP instruction
- ▲ [L]
- Load Immediate instruction format 1 (unconditional transfer)
- Load Immediate instruction format 2 (conditional transfer)
- LOOP BOTTOM instruction format
- Run LOOP program
- ▲ [P]
- PAD interrupt
- ▲ [R]
- RAM page selection
- ▲ [S]
- SCSP
- SCU
- Prohibitions of SCU-DMA indirect mode
- SCU SDRAM select register map
- SCU SDRAM selection bit
- SCU overview
- SCU control register
- SCU version register
- SCU version register map
- Communication unit between SCU and processor
- Specific example of transfer between SCU and processor
- SCU mapping (Cashe_address)
- SCU mapping (Cashe_through_address)
- SCU register map
- SMPC
- SMPC interrupt
- ▲ [V]
- VDP1
- VDP2
[Oh] [or] [is] [was] [is] [or] [Ya] [et al.] []- ▲ [A]
- DMA transfer execution example by setting the address addition value
- Difference in DMA operation depending on the address update bit
- Arithmetic instruction format
- Operand execution method
- ▲ [ka]
- Difference in timing due to external weight valid bit setting
- Write address addition value
- Specifying the write address addition value
- Indirect mode DMA transfer flow
- Details of activation factors
- Operation explanation at the time of cache hit
- ▲ [Sa]
- Sound-Request interrupt
- Execution of subroutine program
- system configuration diagram
- Sprite drawing end interrupt
- ▲ [ta]
- Timer 0 compare register
- Timer 0 compare register map
- Timer 0 interrupt generation process
- Timer 1 set data register
- Timer 1 set data register map
- Timer 1 generation Selection details
- Timer 1 mode register
- Timer 1 mode register map
- Timer 1 interrupt generation process (synchronized with timer 0)
- Timer 1 interrupt generation process (asynchronous with timer 0)
- Timer operation details
- Timer register
- Direct mode DMA transfer operation details
- data
- Data writing example (indirect mode)
- Execution of special processing
- ▲ [ha]
- Blanking interrupt details
- Block Diagram
- ▲ [Ma]
- Main CPU
- DMA transferable area when booted from the main CPU
- Instruction list
- ▲ [ya]
- Read address addition value
- Spare space Normal cycle setting value
- Spare space bus size setting value
- Spare space burst cycle setting
- Spare space burst length setting
- ▲ [Ra]
- Timing when precharge insertion bit is set after writing
- Timing when precharge insertion bit is set after reading
- Level 0 Number of bytes transferred
- Level 2-0 DMA allow bits
- Level 2-0 DMA set register map
- Level 2-0 DMA mode, address update, start factor selection register
- Level 2-0 address addition value
- Level 2-0 write address
- Level 2-0 read address
- Level 2-1 Number of bytes transferred
- ▲ [Wa]
- Contents of work RAM area
- Interrupt status bit content
- Interrupt status register
- Interrupt status register map
- Interrupt control register
- Interrupt mask register
- Interrupt mask register map
- Interrupt factor
- Generic term for interrupt factors
★ HARDWARE Manual ★ SCU User's Manual
Copyright SEGA ENTERPRISES, LTD., 1997