▲ [Back]


"Sega Saturn Overview Manual"

■ No. 1 : [Correction] ・ Overall ■ No. 2 : [Addition] ・ "Chapter 3 Functions" ■ 3.1 CPU Note 
■ No. 3 : [Addition] ・ "Chapter 3 Functions" ■ 3.2 SCU ● Functions 



"SCU User's Manual"

■ No. 1 : [Modify] ・ Chapter 1 Overview ・ ■ 1.2 SCU Mapping ■ No. 2 : [Modify] ・ Chapter 1 Overview ・ ■ 1.3 SCU Register Map ■ No. 3 : [Addition] ・ Chapter 1 Overview・ ■ 1.3 SCU register map ■ No. 4 : [Deleted] ・ Chapter 1 overview ・ ■ DMA forced stop register ■ No. 5 : [Deleted] ・ Chapter 1 overview ・ ■ DMA status register ■ No. 6 : [Addition] ] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ・
■ No. 7 : [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ■ No. 8 : [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ■ No. 9 : [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ・ ◆ Specific usage example ・ ● Indirect mode 
■ No.10 : [Modify] ・ Chapter 3 Register Details ・ ■ 3.1 Register List ■ No.11 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.1 Register List ■ No.12 : [Modify] ・ Chapter 3 Register details ・ ■ 3.2 DMA control register ・ ● Number of bytes transferred 
■ No.13 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ■ No.14 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ■ No.15 : [Addition] ・ No. Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ■ No.16 : [Deleted] ・ Chapter 3 Register Details ■ No.17 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ■ No.18 : [ Addition] ・ Chapter 3 Register Details ・ ■ 3.3 DMA Control Port ■ No.19 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.5 Interrupt Control Register ■ No.20 : [Modify] ・ Chapter 3 Register Details ・ ■ 3.5 Interrupt Control Register ■ No.21 : [Deleted] ・ Chapter 3 Register Details ・ ■ 3.6 A-Bus Control Register ■ No.22 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.6 A-Bus Control Register ■ No .23 : [Addition] ・ Chapter 3 Register Details ・ ■ 3.7 SCU Control Register ■ No.24 : [Modify] ・ Chapter 4 DSP Control ・ ■ 4.2 Instruction List
 "SCSP User's Manual"

■ No. 1 : [Modification] ・ Chapter 1 Sound system configuration ■ No. 2 : [Addition] ・ Chapter 2 SCSP overview ・ ■ 2.2 LSI specifications ・ ● Sound CPU specifications 
■ No. 3 : [Modify] ・ Chapter 4 SCSP Register ・ 4.1 Register Map ・ ■ SCSP Control Register ■ No. 4 : [Change] ・ Chapter 4 SCSP Register ・ 4.1 Register Map ・ ■ SCSP Control Register ■ No. 5 : [Delete] ・ Chapter 4 SCSP register ・ 4.1 Register map ・ ■ SCSP control register ■ No. 6 : [Change] ・ Chapter 4 SCSP register ・ ■ 4.2 Sound source register ■ No. 7 : [Delete] ・ Chapter 4 Chapter SCSP Register ・ ■ 4.2 Sound Source Register ■ No. 8 : [Addition] ・ Chapter 4 SCSP Register ・ ■ 4.2 Sound Source Register ■ No. 9 : [Deleted] ・ Chapter 4 SCSP Register ・ ■ 4.2 Sound Source Register
 "SMPC User's Manual"

■ No. 1 : [Modification] ・ Chapter 1 Overview ・ ■ 1.1 System Configuration ■ No. 2 : [Addition] ・ Chapter 1 Overview ・ ■ 1.2 SH-2 Interface ・ ◆ Parallel I / O Register ■ No. 3 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.1 Command list ■ No. 4 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.2 Command issuance ■ No. 5 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.1 Command list ■ No. 6 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ■ No. 7 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ■ No. 8 : [Addition] ・ Chapter 2 SMPC Command ・ ■ 2.3 Reset System Management Command ■ No. 9 : [Modify] ・ Chapter 2 SMPC Command ・ ■ 2.3 Reset System Management Command ■ No. 10 : [Addition] ・ Chapter 2 Chapter 2 SMPC Command ・ ■ 2.3 Reset System Management Command ■ No.11 : [Addition] ・ Chapter 2 SMPC Command ・ ■ 2.3 Reset System Management Command ■ No.12 : [Addition] ・ Chapter 2 SMPC Command ・ ■ 2.3 Reset system management command ■ No.13 : [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ■ No.14 : [Correction] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ■ No.15 : [Correction] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ■ No.16 : [Correction] ・ Chapter 2 SMPC command ・ ■ 2.4 Non-reset system management command ■ No.17 : [Addition] ・ Chapter 3 Peripheral Control ・ 3.1 SMPC Control Mode ・ ◆ Details of Result Parameters ■ No.18 : [Addition] ・ Chapter 3 Peripheral Control ・ 3.1 SMPC Control Mode ・ ◆ SH-2 Direct Mode ■ No.19 : [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.2 Saturn Peripheral Standard Format C Control Mode ■ No.20 : [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 Support Peripheral Data Format ■ No.21 : [Modify] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Shuttle Mouse ■ No.22 : [Modify] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Sega Saturn Standard Pat ■ No.23 : [Modify] ・ Chapter 3 Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Mission Stick ■ No.24 : [Modify] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Sega Saturn Keyboard ■ No.25 : [Modify] ・ Chapter 3 Peripheral Control ・ ■ 3.3・ ◆ Multi-terminal 6
■ No.25 : [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Multi-Controller ■ No.27 : [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Twin Stick ■ No.28 : [Addition]・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Racing Controller ■ No.29 : [Modify] ・ Chapter 3 Peripheral Control ・ ■ 3.4 Peripheral Access Protocol ■ No.30 : [Deleted] ・ Chapter 3 Peripheral Control ・ ■ 3.4 Peripheral access protocol
 "VDP1 User's Manual"

■ No. 1 : [Modify] ・ Chapter 5 Table ・ ■ 5.2 Color Lookup Table ■ No. 2 : [Modify] ・ Chapter 7 Command ・ ■ 7.8 Polyline Drawing Command
 "VDP2 User's Manual"

■ No. 1 : [Addition] ・ Chapter 1 VDP2 function ・ ■ 1.2 Address map ■ No. 2 : [Addition] ・ Chapter 1 VDP2 function ・ ■ 2.1 TV screen mode ■ No. 3 : [Addition] ・Chapter 1 VDP2 Functions ・ ■ 2.1 TV Screen Mode ■ No. 4 : [Addition] ・ Chapter 2 TV Screen ・ ■ 2.5 External Signals and Scanning Status ■ No. 5 : [Correction] ・ Chapter 2 TV Screen ・ ■ 2.5 External signal and scanning status ■ No. 6 : [Addition] ・ Chapter 2 TV screen ・ ■ 3.2 VRAM bank division ■ No. 7 : [Modification] ・ Chapter 3 RAM ・ ■ 3.3 VRAM access method during display period ■ No. 8 : [Addition] ・ Chapter 4 Scroll screen ・ ■ 3.3 VRAM access method during the display period ■ No. 9 : [Addition] ・ Chapter 8 Window ・ ■ 8.1 Window area ■ No. 10 : [Addition] ・Chapter 9 Sprite Data ・ ■ 9.1 Sprite Data ■ No.11 : [Addition] ・ Chapter 14 Shadow Function ・ ■ 14.1 Shadow Processing ■ No.12 : [New] ・ VDP2 User's Manual


"Sega Saturn Overview Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Correction] ・Incorrect description of the entire frequency unit "KC"
Positive "KHz"
-------------------------------------------------- ---------------------------
■ No. 2: [Addition] ・ "Chapter 3 Functions" ■ 3.1 CPU Note
Added "Table 3.1.1 SH-2 Clock Details" ------------------------------------ -----------------------------------------
■ No. 3: [Addition] ・ "Chapter 3 Functions" ■ 3.2 SCU ● Functions
Added "Table 3.2.1 SCU-DMA clock details" to the "Operating frequency" section. -------------------------------------------------- ---



"SCU User's Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Correction] ・ Chapter 1 Overview ・ ■ 1.2 SCU Mapping ↓ p4, p6
Figure 1.3 SCU mapping (cashe_address) and Figure 1.5 SCU mapping (Cashe_through_address) Medium-Split "SOUND area" into "SOUND RAM area" and "SCSP register area"-"VDP1 area / 192Kbyte" → 768Kbyte
Wrong ├───────────┤　
│ SOUND area │ Approximately 1Mbyte　
│ │　
│ │　
├───────────┤　
├───────────┤　
│ VDP1 area │ 192Kbyte　

Positive ├───────────┤　
│ SOUND RAM area │ Approximately 1Mbyte　
├───────────┤　
│ SCSP register area │　
├───────────┤　
├───────────┤　
│ VDP1 area │ 768Kbyte　
-------------------------------------------------- ---------------------------
■ No. 2: [Correction] ・ Chapter 1 Overview ・ ■ 1.3 SCU Register Map ↓ p7
Figure 1.6 SCU register map
・ "DMA forced stop register" → "Unused"
・ "DMA status register" → "Unused"
-------------------------------------------------- ---------------------------
■ No. 3: [Addition] ・ Chapter 1 Overview ・ ■ 1.3 SCU Register Map ↓ p7
-Added notes after "Fig. 1.6" ------------------------
caution(!)
-Access (read / write) to unused areas is prohibited.
-Be sure to use the cache-through address to access the SCU register.
-------------------------------------------------- ---------------------------
■ No. 4: [Deleted] ・ Chapter 1 Overview ・ ■ DMA forced stop register ↓ p8
Full text deleted ------------------------------------------------ -----------------------------
■ No. 5: [Deleted] ・ Chapter 1 Overview ・ ■ DMA Status Register ↓ p9
Full text deleted ------------------------------------------------ -----------------------------
■ No. 6: [Addition] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ・
↓ p17
-----------------
Figure 2.3 Added (!) DMA notes next to DMA transferable area when booted from DSP ------------------ Added --- ------------
(!) Precautions regarding DMA ● Write protection to A-Bus by SCU-DMA 
Writing to A-Bus by SCU-DMA cannot be used.

● Write protection by SCU-DMA from VDP2 area 
Writing by SCU-DMA from the VDP2 area cannot be used.

● SCU-DMA cannot be used for WORKRAM-L 
Only WORKRAM-HI (SDRAM: 1Mbyte) can use SCU-DMA with WORKRRAM.

● A-Bus ← → B-Bus DMA access prohibited from CPU running to A-Bub and B-Bus 
Access to A-Bus and B-Bus from the CPU is prohibited during DMA operation from A-Bus to B-Bus and from B-Bus to A-Bus. This is because during the weighting, the SDRAM may not be refreshed and may hang.

● Waiting for A-Bus ← → B-Bus SCU-DMA to start when writing to A-Bus and B-Bus by CPU 
CPU write processing to A-Bus and B-Bus has priority over starting SCU-DMA of A-Bus and B-Bus.
For example, when continuous write is executed on the CPU for VDP1 (B-Bus), continuous write ends even if SCU-DMA is started from A-Bus to VDP2 (B-Bus). SCU-DMA will not start until you do.
However, CPU access to A-Bus and B-Bus is waited for while SCU-DMA is running.

● 2 channels can be used simultaneously for DMA 
Up to 2 channels can be used simultaneously with guaranteed DMA priority.
If 3 channels are used at the same time, the priority will be ignored. (DSP DMA instructions are also counted as one channel)

● Do not start DMA level 2 while DMA level 1 is running 
Starting DMA level 2 while DMA is running at level 1 may cause a malfunction.
As a countermeasure, do not start DMA level 2 while starting with DMA level 1.

● Write protection for the corresponding level while DMA is running 
The contents of the DMA mode, address update, activation factor selection register, and addition value register must not be rewritten during DMA activation at that level.
It hangs when rewritten.

● Prohibitions of SCU-DMA indirect mode 
Prohibits the use of SCU-DMA indirect mode for reading from the CD buffer.
Perform SCU-DMA direct mode, CPU-DMA or software transfer.
For transfers that use the A-BUS space as the source as well as the CD buffer, only "4 byte addition" can be specified for the source read address addition value, and the setting of "do not add" is prohibited.
There is no such limitation for SCU-DMA direct mode.
-------------------------------------------------- ---------------------------
■ No. 7: [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ↓ p20
Figure 2.6 The order in which the parameters in the "execution address storage buffer" in the indirect mode DMA transfer operation details are set has been changed.
Incorrect ~ read address ~ number of bytes transferred　
Write address of ~ → Write address of ~ Number of bytes transferred of ~ Read address of ~ -------------------------------- ---------------------------------------------
■ No. 8: [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ↓ p23
◆ Specific usage example ・ ● Indirect mode 
Incorrect replacement of all numerical values of (number of bytes transferred) and (destination address) in "Fig. 2.8 Example of data writing" Correct ┏━━━━━━━━━━┓ ┏━━━━━━━━━ ━┓
┃ 4000000H ┃ → ┃ 20H ┃
┠──────────┨┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨┠──────────┨
┃ 20H ┃ → ┃ 4000000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 5E00000H ┃ → ┃ 10H ┃
┠──────────┨┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨┠──────────┨
┃ 10H ┃ → ┃ 5E00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ DA00000H ┃ → ┃ 15H ┃
┠──────────┨┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨┠──────────┨
┃ 15H ┃ → ┃ DA00000H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ ┃ ┃ ┃
-------------------------------------------------- ---------------------------
■ No. 9: [Correction] ・ Chapter 2 Operation explanation ・ ■ 2.1 DMA transfer ・ ◆ Specific usage example ・ ● Indirect mode
↓ p24
Incorrect replacement of all values of (number of bytes transferred) and (destination address) in "Fig. 2.9 Contents of work RAM area" Correct ┏━━━━━━━━━━┓ ┏━━━━━━━ ━━━┓
┃ 20H ┃ → ┃ 4000000H ┃
┠──────────┨┠──────────┨
┃ 5C00000H ┃ ┃ 5C00000H ┃
┠──────────┨┠──────────┨
┃ 4000000H ┃ → ┃ 20H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 10H ┃ → ┃ 5E00000H ┃
┠──────────┨┠──────────┨
┃ 6080000H ┃ ┃ 6080000H ┃
┠──────────┨┠──────────┨
┃ 5E00000H ┃ → ┃ 10H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 15H ┃ → ┃ DA00000H ┃
┠──────────┨┠──────────┨
┃ 6081000H ┃ ┃ 6081000H ┃
┠──────────┨┠──────────┨
┃ DA00000H ┃ → ┃ 15H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 30H ┃ → ┃ 5000000H ┃
┠──────────┨┠──────────┨
┃ 6090000H ┃ ┃ 6090000H ┃
┠──────────┨┠──────────┨
┃ 5000000H ┃ → ┃ 30H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
┃ 25H ┃ → ┃ D100000H ┃
┠──────────┨┠──────────┨
┃ 60A0000H ┃ ┃ 60A0000H ┃
┠──────────┨┠──────────┨
┃ D100000H ┃ → ┃ 25H ┃
┣━━━━━━━━━━┫ ┣━━━━━━━━━━┫
-------------------------------------------------- ---------------------------
■ No.10: [Correction] ・ Chapter 3 Register Details ・ ■ 3.1 Register List ↓ p40
"Table 3.1 Register List"
"DMA forced stop register" in "DMA control register", "DMA status register" → Delete ----------------------------- ------------------------------------------------
■ No.11: [Addition] ・ Chapter 3 Register Details ・ ■ 3.1 Register List ↓ p40
"Caution" after "Table 3.1 Register List"
Add.
----------------addition----------------
(!) Be sure to use the cache-through address to access the SCU registers.
-------------------------------------------------- ---------------------------
■ No.12: [Correction] ・ Chapter 3 Register details ・ ■ 3.2 DMA control register ・ ● Number of bytes transferred
↓ p42
Incorrect after "Fig. 3.3 Level 0 Number of Transferred Bytes" and after "Fig. 3.4 Level 2-1 Number of Transferred Bytes" D0Cxx-0 (R / W) DMA level ~
Positive D0Cxx-0 (W) DMA level ~
-------------------------------------------------- ---------------------------
■ No.13: [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ↓ p42
Added a note about "● Number of bytes transferred".
---------------addition---------------
(!) Do not read the number of transferred bytes in the DMA transfer register ------------------------------------- ----------------------------------------
■ No.14: [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ↓ p42
Added " ■ Operation when the number of DMA transfer bytes is set to '0' " --------------- Added ---------------
■ Operation when the number of DMA transfer bytes is set to '0' 
When the number of transfer bytes of SCU-DMA is set to '0', the number of transfers is the maximum value for each setting.
detail: 
Developer's Information STN-39 / SCU-DMA Supplement on the number of bytes transferred ---------------------------------- -------------------------------------------
■ No.15: [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ↓ p45
Added " <Restrictions on addition value register> " to "● Addition value register".
-----------------
<Restrictions on addition value register>
(Omitted below)
-------------------------------------------------- ---------------------------
■ No.16: [Deleted] ・ Chapter 3 Register Details ↓ p47-50
"DMA forced stop register", "DMA status register" → Delete ------------------------------------ -----------------------------------------
■ No.17: [Addition] ・ Chapter 3 Register Details ・ ■ 3.2 DMA Control Register ↓ p52
Added notes about "◆ DSP program control port".
------------------------------------
(!) When reading the DSP program control port
Please note that the following phenomena occur.

1. The V flag (overflow flag) is cleared.
The V flag cannot be checked during DSP execution.

2. The DSP end interrupt factor may not occur.
If the program end interrupt flag is monitored (read) during DSP execution, the DSP end interrupt may not occur. Therefore, do not read this address in the case of a program that obtains the DSP end by an interrupt.
-------------------------------------------------- ---------------------------
■ No.18: [Addition] ・ Chapter 3 Register details ・ ■ 3.3 DMA control port ↓ p52
Added notes about "◆ DSP data RAM data port".
------------------------------------
(!) Caution Data RAM Precautions If the pause function (EP) and the one-step execution function (ES) of the DSP program control port are used during DSP execution, the data in the data RAM inside the DSP is not guaranteed. Therefore, please strictly observe the following items.

1. The DSP pause function (EP) and one-step execution function (ES) are prohibited from being used in actual applications.
(These functions are originally for debugging, and the ones used when debugging the DSP will work, but the contents of the data RAM inside the DSP will not be guaranteed.)

2. For access to the DSP data RAM address port and DSP data RAM data port, check that the program execution control flag (EX) and D0-Bus DMA execution flag (T0) of the DSP control port are both "0". Please issue it afterwards.
-------------------------------------------------- ---------------------------
■ No.19: [Addition] ・ Chapter 3 Register Details ・ ■ 3.5 Interrupt Control Register ↓ p57
Added a note about "A-Bus interrupt mask bit".
------------------------------------
(!) Note Be sure to mask the A-Bus interrupt mask bit (set "1") except for the control of a special cartridge connector.

 supplement: 
"Special cartridge equipment" refers to "XBAND modem" and "NetLink modem".
Applications that use these devices should not mask A-Bus external interrupts.
-------------------------------------------------- ---------------------------
■ No.20: [Correction] ・ Chapter 3 Register Details ・ ■ 3.5 Interrupt Control Register ↓ p58
Corrected the description of "◆ Interrupt status register".
Mistakes after Figure 3.22 These status registers are ~
When writing to the positive interrupt status register, the bit that should be set as an interrupt generation may not be set. Therefore, writing to this register is prohibited.
-------------------------------------------------- ---------------------------
■ No.21: [Deleted] ・ Chapter 3 Register Details ・ ■ 3.6 A-Bus Control Register ↓ p62 ~
The following bits of "◆ A-Bus setting register" have been deleted.
p62 ・ CS0 space look-ahead valid bit p66 ・ CS1 space look-ahead valid bit p68 ・ CS2 space look-ahead valid bit p70 ・ Preliminary space look-ahead valid bit ------------------ -------------------------------------------------- ---------
■ No.22: [Addition] ・ Chapter 3 Register Details ・ ■ 3.6 A-Bus Control Register ↓ p72
Addition of notes to "◆ A-Bus refresh register" ----------------------------
(!) The user cannot change the A-Bus refresh output valid bit.
-------------------------------------------------- ---------------------------
■ No.23: [Addition] ・ Chapter 3 Register Details ・ ■ 3.7 SCU Control Register ↓ p72
Added <Supplementary information about initial values> to "◆ SDRAM selection register" -------------------------------
<Supplementary information about initial values> 
The SDRAM selection bit is set to 2M bits x 2 (RSEL = 0) by power-on reset.
You need to reset it to RSEL = 1 and change it to 4M bits x 2.
This setting change is done in the BOOT-ROM, so the user does not need to change it.
-------------------------------------------------- ---------------------------
■ No.24: [Correction] ・ Chapter 4 DSP control ・ ■ 4.2 Instruction list ↓ p84
Wrong ● Constant description Correct ● DSP program description
For a description of constants or assembler, see the Appendix "SCU DSP Arambler User's Manual".
 Please refer to.
-------------------------------------------------- ---------------------------



"SCSP User's Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Correction] ・ Chapter 1 Sound system configuration ↓ p1 to p8
Replaced all "Chapter 1" ------------------------------------------ -----------------------------------
■ No. 2: [Addition] ・ Chapter 2 SCSP Overview ・ ■ 2.2 LSI Specifications ・ ● Sound CPU Specifications
↓ p11
Added to "■ 2.2 LSI specifications" -------------------------------
Note 1: 
Some orders are prohibited in Sega Saturn. 
・ RESET instruction ・ TAS instruction 
-------------------------------------------------- ---------------------------
■ No. 3: [Correction] ・ Chapter 4 SCSP register ・ 4.1 Register map ・ ■ SCSP control register ↓ p28
Incorrect in "Table 4.3 SCSP Common Control Register" ──┬──┬──┬──┬──┬──┬─
− │ OF │ OE │ IO │ IF │ IE │
──┴──┴──┴──┴──┴──┴─
Positive ──┬──┬──┬──┬──┬──┬─
−−│ OF │ OE │ IO │ IF │ −− │
──┴──┴──┴──┴──┴──┴─
-------------------------------------------------- ---------------------------
■ No. 4: [Change] ・ Chapter 4 SCSP Register ・ 4.1 Register Map ・ ■ SCSP Control Register ↓ p29
Previous "Table 4.4 SCSP Common Control Register"
After "List 4.2 SCSP Common Control Register"
-------------------------------------------------- ---------------------------
■ No. 5: [Deleted] ・ Chapter 4 SCSP Register ・ 4.1 Register Map ・ ■ SCSP Control Register ↓ p29
In "List 4.2 SCSP common control register"・ MIEMP: Input FIFO empty → Delete -------------------------------- ---------------------------------------------
■ No. 6: [Change] ・ Chapter 4 SCSP register ・ ■ 4.2 Sound source register ↓ p34
Previous "Table 4.9 Sound source register allocation data"
After "List 4.7 Sound source register allocation data"
-------------------------------------------------- ---------------------------
■ No. 7: [Deleted] ・ Chapter 4 SCSP register ・ ■ 4.2 Sound source register ↓ p29
Description of the "SBCTL" bit in the "■ Loop control register" error Specifies the bit inversion operation for sound input data.
Specifies the bit inversion operation excluding the sign bit of the positive sound input data.
-------------------------------------------------- ---------------------------
■ No. 8: [Addition] ・ Chapter 4 SCSP register ・ ■ 4.2 Sound source register ↓ p89
Added notes in "■ Sound memory configuration register".
-------------------------
Note (!) Be sure to set "1" in this system.
-------------------------------------------------- ---------------------------
■ No. 9: [Deleted] ・ Chapter 4 SCSP register ・ ■ 4.2 Sound source register ↓ p29
Deleted the entire description of "MIEMP (R); Midi Input EMPty " in "■ MIDI Register".
-------------------------------------------------- ---------------------------




"SMPC User's Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Correction] ・ Chapter 1 Overview ・ ■ 1.1 System configuration ↓ p4
Wrong "● Input Peripheral" ■ PAD
Correct ------------------------------
● Input peripheral ◆ Sega Saturn standard pad 
Digital standard pads for Sega Saturn are top, bottom, left, right, A, B, C, X, Y, Z, L,
Equipped with R and start buttons.
◆ Multi controller 
The multi-controller is equipped with analog keys and analog LR buttons while maintaining compatibility with the Sega Saturn standard pad. 
Reference: STN-43 "Multi Controller User's Manual Ver1.00"
◆ Mission stick 
Reference: STN-34 "Analog Mission Stick Manual"
◆ Racing controller 
Reference: STN-38 "Racing Controller Manual"
◆ Shuttle mouse 
Reference: STN-44 "Supplementary explanation of shuttle mouse"
◆ Sega Saturn keyboard 
Reference: STN-45 "Supplementary explanation of Saturn keyboard"
◆ Virtual Gun 
Reference: STN-41 "Virtual Gun User's Manual Ver1.00"
-------------------------------------------------- ---------------------------
■ No. 2: [Addition] ・ Chapter 1 Overview ・ ■ 1.2 SH-2 Interface ・ ◆ Parallel I / O Register ↓ p8
Added notes under "Table 1.4 IOSEL Features" ----------------------------
(!) Use of SH-2 direct mode is prohibited.
(Excluding peripherals using SH-2 direct mode)
-------------------------------------------------- ---------------------------
■ No. 3: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.1 Command list ↓ p12
Clarified user prohibition commands in "Table 2.1 Reset System Management Commands". Added under "Table 2.1".
----------------------
X mark indicates prohibition of use by users ------------------------------------------- ----------------------------------
■ No. 4: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.2 Command issuance ↓ p18
"● INTBACK command issuance timing after executing SYSRES, CKCHG320, CKCHG352 commands"
Added notes to ------------------------------
(!) Be sure to use the system library when using the clock change command.
-------------------------------------------------- ---------------------------
■ No. 5: [Addition] ・ Chapter 2 SMPC Command ・ ■ 2.1 Command List ↓ p20
Clarified user-prohibited commands in "Table 2.5 SH-2 Command Issuance Restrictions". Added under "Table 2.5".
----------------------
X mark indicates prohibition of use by users ------------------------------------------- ----------------------------------
■ No. 6: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p22
"No.1 MSHON" command, added attention to remarks column ------------------------
remarks 
The use of users is prohibited.
-------------------------------------------------- ---------------------------
■ No. 7: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p24
"No.3 SSH OFF" command, remarks column added ------------------------
remarks 
Issuing this command is prohibited under the following conditions. 
When the slave SH-2 is accessing the external bus (A-Bus, B-Bus, CPU-Bus).
In other words, it cannot be used except when the slave SH-2 is accessing only the cache inside the CPU.
If the above management is difficult on the application side, use the system library clock change (SYS_CHGSYSCK).
-------------------------------------------------- ---------------------------
■ No. 8: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p25
"No.4 SNDON" command, remarks column added ------------------------
remarks 
See "Sound OFF" command.
-------------------------------------------------- ---------------------------
■ No. 9: [Correction] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p26
"No.5 SNDOFF" command, full text correction in remarks ------------------------
remarks 
When stopping the sound CPU, be sure to strictly observe the following restrictions.
<< Restrictions on stopping and starting sound blocks >>
The sound block must be stopped and there must be no non-access period of 0.5 seconds or more from the main system (SH2 side) to the sound RAM.
If you want to stop the sound block, load the sound driver, etc. 
Stop it for the minimum required period and restart it immediately.
If you do not need to use the sound CPU (MC68EC000), a dummy program 
It is necessary to take measures such as executing (just an infinite loop).
If this restriction is not observed, the operation of sound RAM and sound block cannot be guaranteed.
-------------------------------------------------- ---------------------------
■ No.10: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p27
"No.6 CDON" command, added note to remarks ------------------------
remarks 
The use of users is prohibited.
-------------------------------------------------- ---------------------------
■ No.11: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p28
"No.7 CDOFF" command, added note to remarks ------------------------
remarks 
:
:
The use of users is prohibited.
-------------------------------------------------- ---------------------------
■ No.12: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p29
"No.8 SYSRES" command, added note to remarks ------------------------
remarks 
:
:
The use of users is prohibited.
-------------------------------------------------- ---------------------------
■ No.13: [Addition] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p30
"No.9 CKCHG352" command, added attention to the remarks column ------------------------
remarks 
:
:
The use of users is prohibited.
If used, system library clock change (SYS_CHGSYSCK)
Please use.
-------------------------------------------------- ---------------------------
■ No.14: [Correction] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p33
Corrected the "No. 12 RESENAB" command and function content column. 
Command to enable ~.
In addition, the default when the power is turned on ~

Positive ------------------------
Function content 
Command to enable ~.
The default value when booting with BOOR ROM is enabled. 
-------------------------------------------------- ---------------------------
■ No.15: [Correction] ・ Chapter 2 SMPC command ・ ■ 2.3 Reset system management command ↓ p34
Corrected "No. 13 RESDISA" command and function content column. 
Command to enable ~.
In addition, the default when the power is turned on ~
Positive ------------------------
Function content 
Command to enable ~.
The default value when booting with BOOR ROM is enabled. 
-------------------------------------------------- ---------------------------
■ No.16: [Correction] ・ Chapter 2 SMPC command ・ ■ 2.4 Non-reset system management command ↓ p40
"No.1 INTBACK" command,
Corrected the "● OREG9" area code table,
Changed "5H", "5H", "5H", "5H" to "SEGA RESERVED" ---------------------------- -------------------------------------------------
■ No.17: [Addition] ・ Chapter 3 Peripheral Control ・ 3.1 SMPC Control Mode ・ ◆ Details of Result Parameters ↓ p68
Added "Table 3.7 Multi-tap ID and number of connectors" and "SEGA reservation" ---------------------------------- -------------------------------------------
■ No.18: [Addition] ・ Chapter 3 Peripheral Control ・ 3.1 SMPC Control Mode ・ ◆ SH-2 Direct Mode ↓ p68
Added notes under "● Features" -----------------------
(!) If none of the above features apply
Do not use "SH-2 Direct Mode".

Currently (April 1997), the only peripheral that must use "SH-2 Direct Mode" is "Virtual Gun".
-------------------------------------------------- ---------------------------
■ No.19: [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.2 Saturn Peripheral Standard Format C Control Mode ↓ p68
Added to "● Saturn standard format types and data formats" -------------------------------
● Future expansion of standard format
At the moment, we have prepared the following four formats, but we plan to prepare them one by one when the need arises in the future.

・ Saturn Digital Device ・ Saturn Analog Device ・ Pointing Device ・ Keyboard Device ● Precautions for using standard format
In order to comply with the standard format, when the data size is larger than the standard format, delete the extra data and use it. Also, when the data size is smaller than the standard format, it can be realized by supplementing the missing data with other data.
Also, as an example corresponding on the peripheral side, there is an analog XY control like an analog joystick, but when there is no corresponding digital input, the analog XY data becomes more than a certain value, There is a possibility that the peripheral side will adopt the method of turning the U, D, L, and R bits ON / OFF.
-------------------------------------------------- ---------------------------
■ No.20: [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 Support Peripheral Data Format ↓ p81
List Add list ------------------
・ Mega drive 3 button pad ・ Mega drive 6 button pad ・ Shuttle mouse ・ Sega tap ・ Sega Saturn standard pad ・ Mission stick ・ Sega Saturn keyboard ・ Multi terminal 6
・ Multi controller ・ Twin stick ・ Racing controller ----------------------------------------- ------------------------------------
■ No.21: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Shuttle Mouse ↓ p81
Wrong ■ Saturn Mouse (tentative name)
Positive ◆ Shuttle mouse
-------------------------------------------------- ---------------------------
■ No.22: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Sega Saturn Standard Pat ↓ p82
Wrong ■ Saturn standard PAD (tentative name)
Positive ◆ Sega Saturn standard pad
-------------------------------------------------- ---------------------------
■ No.23: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Mission Stick ↓ p83
Wrong ■ Saturn analog joystick (tentative name)
Positive ◆ Mission stick
-------------------------------------------------- ---------------------------
■ No.24: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Sega Saturn Keyboard ↓ p83
Wrong ■ Saturn keyboard (tentative name)
Positive ◆ Sega Saturn keyboard
-------------------------------------------------- ---------------------------
■ No.25: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Multi-Terminal 6
↓ p85
Wrong ■ Saturn 6P multi-tap (tentative name)
Positive ◆ Multi Terminal 6
-------------------------------------------------- ---------------------------
■ No.26: [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Multi-Controller ↓ p85?
◆ Added multi-controller ------------------------------------------------------------- --------------------------------
■ No.27: [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Twin Stick ↓ p85?
◆ Added twin sticks --------------------------------------------- --------------------------------
■ No.28: [Addition] ・ Chapter 3 Peripheral Control ・ ■ 3.3 ・ ◆ Racing Controller ↓ p85?
◆ Added racing controller --------------------------------------------- --------------------------------
■ No.29: [Correction] ・ Chapter 3 Peripheral Control ・ ■ 3.4 Peripheral Access Protocol ↓ p86
■ 3.4 Peripheral access protocol
Incorrect This section shows the peripheral access protocol and data format in SH-2 direct mode.
Correct This section shows the peripheral access protocol in SH-2 direct mode.
-------------------------------------------------- ---------------------------
■ No.30: [Deleted] ・ Chapter 3 Peripheral Control ・ ■ 3.4 Peripheral Access Protocol ↓ p87
■ 3.4 Deleted the following items and explanations in the peripheral access protocol.
■ About the peripheral interface protocol ■ Procedure for accessing a peripheral with a megadrive peripheral ID other than 5H in SH-2 direct mode ■ Procedure for accessing a peripheral with a megadrive peripheral ID for 5H in SH-2 direct mode The following p90 All subsequent items ---------------------------------------------- -------------------------------




"VDP1 User's Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Correction] ・ Chapter 5 table ・ ■ 5.2 Color look-up table ↓ p62
Incorrect in the explanation of " ■ 5.2 Color Lookup Table " ~, RGB code are both valid. The RGB code is MSB = 0 . The color bank code is ~
Both positive and RGB codes are valid. The RGB code is MSB = 1 . The color bank code is ~
-------------------------------------------------- ---------------------------
■ No. 2: [Correction] ・ Chapter 7 Command ・ ■ 7.8 Polyline drawing command ↓ p128
■ 7.8 Polyline drawing command
False When the end bit is 0B and the command selection bit is 0100B , this is a polyline drawing command.
This is a polyline drawing command when the positive end bit is 0B and the command selection bit is 0101B.
-------------------------------------------------- ---------------------------




"VDP2 User's Manual"
-------------------------------------------------- ---------------------------
■ No. 1: [Addition] ・ VDP2 User's Manual ・ Chapter 1 VDP2 Functions ・ ■ 1.2 Address Map ↓ p3
In the explanation of "■ 1.2 Address Map " ● VRAM
Wrong ~ All possible in longword units.
All from positive to longword units are possible. However, read access by SCU-DMA should not be performed.
-------------------------------------------------- ---------------------------
■ No. 2: [Addition] ・ VDP2 User's Manual ・ Chapter 1 VDP2 Functions ・ ■ 2.1 TV screen mode ↓ p12
Added under "Table 2.1 TV Screen Modes" -------------------------------
● High resolution mode The precautions when the TV screen mode is set to high resolution mode are as follows.
-The normal scroll surface (NBG0 to NBG3) is displayed as if the picture when the TV screen mode is in normal mode is reduced to 1/2 in the horizontal direction.
-Although the rotating scroll surface (RBG0,1) can be displayed, the horizontal resolution of the picture is the same as when the TV screen mode is normal mode.
-The VRAM cycle pattern register is valid only for T0 to T3, and T4 to
It is invalid for T7.
-The vertical cell scroll function cannot be used.
-The color calculation function is limited. For details, see "12.1 Color Calculation Function"
  Please refer to.
-The extended color calculation function and blur calculation function cannot be used.
-------------------------------------------------- ---------------------------
■ No. 3: [Addition] ・ VDP2 User's Manual ・ Chapter 1 VDP2 Functions ・ ■ 2.1 TV screen mode ↓ p18
Added below the table of horizontal resolution bits ---------------------------------
There are restrictions on the combination of TV screen mode settings for VDP1 and VDP2.
In addition, the screen display changes depending on the combination of interlace mode settings. 
Table 2.2 shows the restrictions on TV screen mode settings, and Table 2.3 shows the screen displays for each interlaced mode setting. 


	Table 2.2 Restrictions on TV screen mode settings ~


	VDP2 setting (TVMD: HRESO2..0)
	VDP1 setting (TVMR: TVM2..0) Setting permission or disapproval



Normal mode
 (000 or 001)		
	Normal 000 Possible


High resolution 001 Setting prohibited


Rotation 16 010 Possible


Rotation 8 011 Possible


HDTV 100 Setting prohibited



High resolution mode
 (010 or 011)		
	Normal 000 Possible


High resolution 001 Possible


Rotation 16 010 Possible


Rotation 8 011 Possible


HDTV 100 Setting prohibited



Dedicated monitor mode
 (100,101,110,111)		
	Normal 000 Possible


High resolution 001 Setting prohibited


Rotation 16 010 Possible


Rotation 8 011 Possible


HDTV 100 Setting prohibited



	Table 2.3 Screen display by interlace mode setting

	
LSMD value DIE value Display of VDP2 Display of VDP1

	
00 0 Non-interlaced Non-interlaced

	
1 Non-interlaced Cannot be displayed correctly

	
01 0 Monodense interlacing Monodense interlacing

	
1 Monodense interlacing Dense interlace

	
11 0 Dense interlace Monodense interlacing

	
1 Dense interlace Dense interlace

	


-------------------------------------------------- ---------------------------
■ No. 4: [Addition] ・ VDP2 User's Manual ・ Chapter 2 TV screen ・ ■ 2.5 External signal and scanning status ↓ p22
" " V blank flag: Vertical blank flag (VBLANK), bit 3 "
Additional text -------------------------------------------
This bit has a TV screen display bit (DISP) of 1 in the TV screen mode register.
It is valid only when. V when the TV screen display bit (DISP) is 0
The blank flag (VBLANK) is always 1.
-------------------------------------------------- ---------------------------
■ No. 5: [Correction] ・ VDP2 User's Manual ・ Chapter 2 TV screen ・ ■ 2.5 External signal and scanning status ↓ p24
Incorrect in "Table 2.4 V Counter Register Bit Contents" Normal │ │ │ │ │ │ │ │ │ │ │ │ │
High resolution │ V8 │ V7 │ V6 │ V5 │ V4 │ V3 │ V2 │ V1 │ V0 │ invalid │
・ ・ ・ │ │ │ │ │ │ │ │ │ │ │ │ │
Normal Normal │ │ │ │ │ │ │ │ │ │ │ │ │
High resolution │ V9 │ V8 │ V7 │ V6 │ V5 │ V4 │ V3 │ V2 │ V1 │ V0 │
・ ・ ・ │ │ │ │ │ │ │ │ │ │ │ │ │
-------------------------------------------------- ---------------------------
■ No. 6: [Addition] ・ VDP2 User's Manual ・ Chapter 2 TV screen ・ ■ 3.2 VRAM bank division ↓ p30
Added "● Pattern name data storage location" -------------------------
● Storage location of pattern name data The storage location of pattern name data on the scroll surface has the following restrictions regardless of the normal scroll surface or the rotating scroll surface.
Table 3.2 below shows the restrictions on VRAM mode bits and pattern name data storage locations.
There are no restrictions on the storage location of character pattern data or bitmap pattern data.

1. 1. When neither VRAM-A nor VRAM-B is divided into two, it can be stored in either VRAM-A or VRAM-B. When dividing only VRAM-A into two a) When storing in VRAM-B, it may be stored in VRAM-A1 b) When not storing in VRAM-B, store in either VRAM-A0 or A1 May 3. When dividing only VRAM-B into two a) When storing in VRAM-A, it may be stored in VRAM-B1 b) When not storing in VRAM-A, store in either VRAM-B0 or B1 May 4. When both VRAM-A and VRAM-B are divided into two, they can be stored in either VRAM-A0 or VRAM-B0 and either VRAM-A1 or VRAM-B1.


	Table 3.2 Restrictions on pattern name data storage location

	
VRAM mode bit setting
 Pattern name data storage location

	
VRAMD VRBMD VRAM-A VRAM-B

	
VRAM-A0 VRAM-A1 VRAM-B0 VRAM-B1

	
0 0 ○ ×

	
× ○

	
1 0 × ○ ○

	
○ ○ ×

	
0 1 ○ × ○

	
× ○ ○

	
1 1 ○ ○ × ×

	
○ × × ○

	
× ○ ○ ×

	
× × ○ ○

	

○: Can be stored ×: Cannot be stored [Note] If there are multiple locations that can be stored, it is not necessary to store them in all ------------------------ -------------------------------------------------- ---
■ No. 7: [Correction] ・ VDP2 User's Manual ・ Chapter 3 RAM ・ ■ 3.3 VRAM access method during the display period ↓ p34
Corrected "Table 3.4 Character pattern data read access specification restrictions" in "● Image data access" Incorrect <Omitted>
Normal Table 3.4 Character pattern data read access specification restriction


item
 TV screen mode
 Character size
 Access timing of pattern name table data


T0
 T1
 T2
 T3
 T4
 T5
 T6
 T7



Timing when character pattern table data access can be specified


normal


1 horizontal cell x 1 vertical cell 2 horizontal cells x 2 vertical cells


T0 to T2,
 T4 ~ T7
 T0 to T3,
 T5 ~ T7
 T0 to T3,
 T6 ~ T7
 T0 to T3,
 T7
 T0 to T3
 T1 ~ T3
 T2, T3
 T3





High resolution,
 Dedicated monitor


1 horizontal cell x 1 vertical cell


T0 to T2
 T1 ~ T3
 T0,
 T2, T3
 T0, T1,
 T3
 −
 −
 −
 −





2 horizontal cells x 2 vertical cells


T0 to T2
 T1 ~ T3
 T2, T3
 T3
 −
 −
 −
 −



-------------------------------------------------- ---------------------------
■ No. 8: [Addition] ・ VDP2 User's Manual ・ Chapter 4 Scroll screen ・ ■ 3.3 VRAM access method during the display period ↓ p34
Additional explanation to "◆ Limitation of left / right inversion function bit" is shown in.
------------------------
◆ Limitation of left / right inversion function bits The inversion function bits of NBG0 and NBG1 have 16 character colors.
Valid only for colors or 256 colors. Do not set it to 1 for other character colors.
-------------------------------------------------- ---------------------------
■ No. 9: [Addition] ・ VDP2 User's Manual ・ Chapter 8 Window ・ ■ 8.1 Window area ↓ p183
Additional explanation under "Table 8.2 Bit contents of window position register for vertical coordinates" ------------------------------ ----- -----
Window position Vertical end point coordinate value limit 
When using the normal window in the dense interlaced mode, set the value of the vertical end point coordinate window position register (WPEY0: 1800C6H, WPEY: 1800CEH) to "1FCH ~ 1".
Do not set it to "FFH".
Entering these values disables the window.
-------------------------------------------------- ---------------------------
■ No.10: [Addition] ・ VDP2 User's Manual ・ Chapter 9 Sprite Data ・ ■ 9.1 Sprite Data ↓ p204
Added "● Normal Shadow Sprite" after "● Sprite Color Mode" ------------------------------ ---
● Normal shadow sprite When using a palette-type sprite, the sprite may not be displayed depending on the sprite character's pixel data and color bank value (dot color data in the VDP2 hardware manual).
This is because the dot data is judged as the dot data (normal shadow data) for the shadow function of VDP2. Table 9.2 shows the sprite data that is judged as normal shadow data depending on the sprite type setting of VDP2.
"14.1 Shadow Processing" and "6.4" in the VDP1 Hardware Manual
See CMDCOLR (Color Control Word).




Sprite type Number of colors Palette code Color bank


Types 0-3, 5

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx x111 1111 0000
 xxxx x111 11xx 0000
 xxxx x111 1xxx 0000
 xxxx x111 xxxx 0000



Types 4, 6

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx xx11 1111 0000
 xxxx xx11 11xx 0000
 xxxx xx11 1xxx 0000
 xxxx xx11 xxxx 0000



Type 7

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx xxx1 1111 0000
 xxxx xxx1 11xx 0000
 xxxx xxx1 1xxx 0000
 xxxx xxx1 xxxx 0000



Types C to F

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx xxxx 1111 0000
 xxxx xxxx 11xx 0000
 xxxx xxxx 1xxx 0000
 Not relevant



Type 8

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx xxxx x111 0000
 xxxx xxxx x1xx 0000
 Not relevant



Type 9-B

16
 64
 128
 256


1110
 xx11 1110
 x111 1110
 1111 1110


xxxx xxxx xx11 0000
 Not related Not related Not related



-------------------------------------------------- ---------------------------
■ No.11: [Addition] ・ VDP2 User's Manual ・ Chapter 14 Shadow Function ・ ■ 14.1 Shadow Processing ↓ p258
It can be added or specified in the description of "● MSB Shadow".
---------------------------------
Note that the priority number of the transparent shadow sprite is the value set in the sprite register 0 of the priority number register.
---------------------------------
When using a sprite window, ~
-------------------------------------------------- ---------------------------
■ No.12: [New] ・ VDP2 User's Manual ↓
" Chapter 15 How to use VDP2" is newly added ------------------------------------- ----------------------------------------




▲ [Back]



Copyright SEGA ENTERPRISES, LTD., 1997